Update the Xilinx UltraScale+ demo project to use the BSP and hardware platform gener...

[freertos] / FreeRTOS / Demo / CORTEX_A53_64-bit_UltraScale_MPSoC / RTOSDemo_A53 / src / lscript.ld

diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
index 52c1e882b1cb4ce0db8a2945db354cff6f0731c7..4e2ff8a276a06187a4e383a8df55b2f370a54f86 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld
@@ -22,19 +22,12 @@ _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
 MEMORY\r
 {\r
    psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000\r
-   psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000\r
+   psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x80000000\r
    psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000\r
    psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000\r
    psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000\r
    psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000\r
    psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000\r
-   psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000\r
-   psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000\r
-   psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000\r
-   psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000\r
-   psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000\r
-   psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000\r
-   psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000\r
 }\r
 \r
 /* Specify the default entry point to the program */\r
@@ -58,23 +51,23 @@ SECTIONS
    *(.glue_7t)\r
    *(.ARM.extab)\r
    *(.gnu.linkonce.armextab.*)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .init (ALIGN(64)) : {\r
    KEEP (*(.init))\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .fini (ALIGN(64)) : {\r
    KEEP (*(.fini))\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .interp : {\r
    KEEP (*(.interp))\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .note-ABI-tag : {\r
    KEEP (*(.note-ABI-tag))\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .rodata : {\r
    . = ALIGN(64);\r
@@ -83,7 +76,7 @@ SECTIONS
    *(.rodata.*)\r
    *(.gnu.linkonce.r.*)\r
    __rodata_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .rodata1 : {\r
    . = ALIGN(64);\r
@@ -91,7 +84,7 @@ SECTIONS
    *(.rodata1)\r
    *(.rodata1.*)\r
    __rodata1_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .sdata2 : {\r
    . = ALIGN(64);\r
@@ -100,7 +93,7 @@ SECTIONS
    *(.sdata2.*)\r
    *(.gnu.linkonce.s2.*)\r
    __sdata2_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .sbss2 : {\r
    . = ALIGN(64);\r
@@ -109,7 +102,7 @@ SECTIONS
    *(.sbss2.*)\r
    *(.gnu.linkonce.sb2.*)\r
    __sbss2_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .data : {\r
    . = ALIGN(64);\r
@@ -121,7 +114,7 @@ SECTIONS
    *(.got)\r
    *(.got.plt)\r
    __data_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .data1 : {\r
    . = ALIGN(64);\r
@@ -129,19 +122,19 @@ SECTIONS
    *(.data1)\r
    *(.data1.*)\r
    __data1_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .got : {\r
    *(.got)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .got1 : {\r
    *(.got1)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .got2 : {\r
    *(.got2)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .ctors : {\r
    . = ALIGN(64);\r
@@ -153,7 +146,7 @@ SECTIONS
    KEEP (*(.ctors))\r
    __CTOR_END__ = .;\r
    ___CTORS_END___ = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .dtors : {\r
    . = ALIGN(64);\r
@@ -165,52 +158,52 @@ SECTIONS
    KEEP (*(.dtors))\r
    __DTOR_END__ = .;\r
    ___DTORS_END___ = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .fixup : {\r
    __fixup_start = .;\r
    *(.fixup)\r
    __fixup_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .eh_frame : {\r
    *(.eh_frame)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .eh_framehdr : {\r
    __eh_framehdr_start = .;\r
    *(.eh_framehdr)\r
    __eh_framehdr_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .gcc_except_table : {\r
    *(.gcc_except_table)\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .mmu_tbl0 (ALIGN(4096)) : {\r
    __mmu_tbl0_start = .;\r
    *(.mmu_tbl0)\r
    __mmu_tbl0_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .mmu_tbl1 (ALIGN(4096)) : {\r
    __mmu_tbl1_start = .;\r
    *(.mmu_tbl1)\r
    __mmu_tbl1_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .mmu_tbl2 (ALIGN(4096)) : {\r
    __mmu_tbl2_start = .;\r
    *(.mmu_tbl2)\r
    __mmu_tbl2_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .ARM.exidx : {\r
    __exidx_start = .;\r
    *(.ARM.exidx*)\r
    *(.gnu.linkonce.armexidix.*.*)\r
    __exidx_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .preinit_array : {\r
    . = ALIGN(64);\r
@@ -218,7 +211,7 @@ SECTIONS
    KEEP (*(SORT(.preinit_array.*)))\r
    KEEP (*(.preinit_array))\r
    __preinit_array_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .init_array : {\r
    . = ALIGN(64);\r
@@ -226,7 +219,7 @@ SECTIONS
    KEEP (*(SORT(.init_array.*)))\r
    KEEP (*(.init_array))\r
    __init_array_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .fini_array : {\r
    . = ALIGN(64);\r
@@ -234,13 +227,13 @@ SECTIONS
    KEEP (*(SORT(.fini_array.*)))\r
    KEEP (*(.fini_array))\r
    __fini_array_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .ARM.attributes : {\r
    __ARM.attributes_start = .;\r
    *(.ARM.attributes)\r
    __ARM.attributes_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .sdata : {\r
    . = ALIGN(64);\r
@@ -249,7 +242,7 @@ SECTIONS
    *(.sdata.*)\r
    *(.gnu.linkonce.s.*)\r
    __sdata_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .sbss (NOLOAD) : {\r
    . = ALIGN(64);\r
@@ -259,7 +252,7 @@ SECTIONS
    *(.gnu.linkonce.sb.*)\r
    . = ALIGN(64);\r
    __sbss_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .tdata : {\r
    . = ALIGN(64);\r
@@ -268,7 +261,7 @@ SECTIONS
    *(.tdata.*)\r
    *(.gnu.linkonce.td.*)\r
    __tdata_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .tbss : {\r
    . = ALIGN(64);\r
@@ -277,7 +270,7 @@ SECTIONS
    *(.tbss.*)\r
    *(.gnu.linkonce.tb.*)\r
    __tbss_end = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .bss (NOLOAD) : {\r
    . = ALIGN(64);\r
@@ -288,7 +281,7 @@ SECTIONS
    *(COMMON)\r
    . = ALIGN(64);\r
    __bss_end__ = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\r
 \r
@@ -304,7 +297,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
    . += _HEAP_SIZE;\r
    _heap_end = .;\r
    HeapLimit = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 .stack (NOLOAD) : {\r
    . = ALIGN(64);\r
@@ -323,7 +316,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
    . += _EL0_STACK_SIZE;\r
    . = ALIGN(64);\r
    __el0_stack = .;\r
-} > psu_r5_ddr_0_S_AXI_BASEADDR\r
+} > psu_ddr_0_S_AXI_BASEADDR\r
 \r
 _end = .;\r
 }\r