Update the Xilinx UltraScale+ 64-bit demo to use the hardware definition and BSP...

[freertos] / FreeRTOS / Demo / CORTEX_A53_64-bit_UltraScale_MPSoC / ZynqMP_hw_platform / .project

diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project
index 7c49632ae8c8a09348c1134ad0c18e8d59c07caf..aab343b6e44df42c9c3623392e6ecec68bbe9d86 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_hw_platform/.project
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>\r
 <projectDescription>\r
-       <name>ZynqMP_hw_platform</name>\r
-       <comment>Created by SDK v2015.1</comment>\r
+       <name>ZynqMP_ZCU102_hw_platform</name>\r
+       <comment>Created by SDK v2016.1</comment>\r
        <projects>\r
        </projects>\r
        <buildSpec>\r
@@ -11,7 +11,7 @@
        </natures>\r
        <filteredResources>\r
                <filter>\r
-                       <id>1436883660925</id>\r
+                       <id>1461845622212</id>\r
                        <name></name>\r
                        <type>6</type>\r
                        <matcher>\r
@@ -20,7 +20,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1436883660925</id>\r
+                       <id>1461845622222</id>\r
                        <name></name>\r
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                        <matcher>\r
@@ -29,7 +29,7 @@
                        </matcher>\r
                </filter>\r
                <filter>\r
-                       <id>1436883660925</id>\r
+                       <id>1461845622222</id>\r
                        <name></name>\r
                        <type>6</type>\r
                        <matcher>\r