SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command console.

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D3x_Xplained_IAR / AtmelFiles / libchip_sama5d3x / cp15 / cp15_asm_iar.s

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s
index 4861c05c47676b5fd3253100de85ec36575bb242..f5827cd2da30904d0f4365747f50dd0935909acd 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s
+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s
@@ -1,5 +1,5 @@
 /* ----------------------------------------------------------------------------\r
- *         SAM Software Package License \r
+ *         SAM Software Package License\r
  * ----------------------------------------------------------------------------\r
  * Copyright (c) 2012, Atmel Corporation\r
  *\r
@@ -26,18 +26,18 @@
  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  * ----------------------------------------------------------------------------\r
  */\r
- \r
+\r
 \r
 /** \file */\r
 \r
 \r
 /** \file */\r
-/** \r
+/**\r
  * \addtogroup cp15_cache Cache Operations\r
  *\r
  * \section Usage\r
  *\r
- * They are performed as MCR instructions and only operate on a level 1 cache associated with \r
+ * They are performed as MCR instructions and only operate on a level 1 cache associated with\r
  * ATM v7 processor.\r
  * The supported operations are:\r
  * <ul>\r
@@ -62,7 +62,7 @@
  * \ref cp15.h\n\r
  * \ref cp15_arm_iar.s \n\r
  */\r
- \r
+\r
 \r
         MODULE  ?cp15\r
 \r
@@ -73,7 +73,6 @@
 /*----------------------------------------------------------------------------\r
  *        Headers\r
  *----------------------------------------------------------------------------*/\r
-#define __ASSEMBLY__\r
 \r
 \r
 /*----------------------------------------------------------------------------\r
@@ -103,10 +102,10 @@
         PUBLIC  CP15_flush_dcache_for_dma\r
         PUBLIC  CP15_flush_kern_dcache_for_dma\r
 \r
-/** \r
+/**\r
  * \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.\r
  *  Reading from this register returns the device ID, the cache type, or the TCM status\r
- *   depending on the value of Opcode_2 used. \r
+ *   depending on the value of Opcode_2 used.\r
  */\r
         SECTION .CP15_ReadID:DATA:NOROOT(2)\r
         PUBLIC   CP15_ReadID\r
@@ -115,7 +114,7 @@ CP15_ReadID:
         mrc     p15, 0, r0, c0, c0, 0\r
         bx      lr\r
 \r
-/** \r
+/**\r
  * \brief Register c1 is the Control Register for the ARM926EJ-S processor.\r
  * This register specifies the configuration used to enable and disable the\r
  * caches and MMU. It is recommended that you access this register using a\r
@@ -125,7 +124,7 @@ CP15_ReadID:
         PUBLIC   CP15_ReadControl\r
 CP15_ReadControl:\r
         mov     r0, #0\r
-        mrc     p15, 0, r0, c1, c0, 0   \r
+        mrc     p15, 0, r0, c1, c0, 0\r
         bx      lr\r
 \r
         SECTION .CP15_WriteControl:CODE:NOROOT(2)\r
@@ -155,8 +154,8 @@ CP15_WriteDomainAccessControl:
         nop\r
         nop\r
         bx      lr\r
- \r
-/** \r
+\r
+/**\r
  * \brief  ARMv7A architecture supports two translation tables\r
  * Configure translation table base (TTB) control register cp15,c2\r
  * to a value of all zeros, indicates we are using TTB register 0.\r
@@ -277,7 +276,7 @@ CP15_CleanDCacheBySetWay:
         bx      lr\r
 \r
 /**\r
- * \brief Clean unified cache line by MVA \r
+ * \brief Clean unified cache line by MVA\r
  */\r
         SECTION .CP15_CleanDCacheMva:CODE:NOROOT(2)\r
         PUBLIC   CP15_CleanDCacheMva\r
@@ -293,7 +292,7 @@ CP15_CleanDCacheMva:
         PUBLIC   CP15_CleanInvalidateDcacheLineByMva\r
 CP15_CleanInvalidateDcacheLineByMva:\r
         mov     r0, #0\r
-        mcr     p15, 0, r0, c7, c14, 1 \r
+        mcr     p15, 0, r0, c7, c14, 1\r
         bx      lr\r
 \r
 /**\r
@@ -317,7 +316,7 @@ CP15_CleanInvalidateDcacheLine:
         PUBLIC   CP15_coherent_dcache_for_dma\r
 CP15_coherent_dcache_for_dma:\r
 //      dcache_line_size r2, r3\r
- \r
+\r
         mrc     p15, 0, r3, c0, c0, 1         // read ctr\r
         lsr     r3, r3, #16\r
         and     r3, r3, #0xf                  // cache line size encoding\r