* In addition to the standard demo tasks, the following tasks and tests are\r
* defined and/or created within this file:\r
*\r
- * FreeRTOS+CLI command console. The command console is access through the\r
- * UART to USB connector on the _RB_. For\r
- * reasons of robustness testing the UART driver is deliberately written to be\r
- * inefficient and should not be used as a template for a production driver.\r
- * Type "help" to see a list of registered commands. The FreeRTOS+CLI license\r
- * is different to the FreeRTOS license, see http://www.FreeRTOS.org/cli for\r
- * license and usage details. The default baud rate is 115200.\r
+ * "FreeRTOS+CLI command console" - The command console is access using the USB\r
+ * CDC driver provided by Atmel. It is accessed through the USB connector\r
+ * marked J6 SAMA5D3 Xplained board. Type "help" to see a list of registered\r
+ * commands. The FreeRTOS+CLI license is different to the FreeRTOS license, see\r
+ * http://www.FreeRTOS.org/cli for license and usage details. The default baud\r
+ * rate is 115200.\r
*\r
* "Reg test" tasks - These fill both the core and floating point registers with\r
* known values, then check that each register maintains its expected value for\r
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
+#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )\r
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
\r
-/* The priority used by the UART command console task. */\r
+/* The initial priority used by the UART command console task. */\r
#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
\r
/* The LED used by the check timer. */\r
/*\r
* The task that manages the FreeRTOS+CLI input and output.\r
*/\r
-extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );\r
+extern void vUSBCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );\r
\r
/*\r
* A high priority task that does nothing other than execute at a pseudo random\r
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
\r
/*-----------------------------------------------------------*/\r
-#warning Check demo and source folders for _RB_\r
+\r
void main_full( void )\r
{\r
/* Start all the other standard demo/test tasks. They have not particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
-//_RB_ vStartInterruptQueueTasks();\r
+ vStartInterruptQueueTasks();\r
vStartDynamicPriorityTasks();\r
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
vCreateBlockTimeTasks();\r
\r
/* Start the tasks that implements the command console on the UART, as\r
described above. */\r
-//_RB_ vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
+ vUSBCommandConsoleStart( mainCDC_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY );\r
\r
/* Register the standard CLI commands. */\r
-//_RB_ vRegisterSampleCLICommands();\r
+ vRegisterSampleCLICommands();\r
\r
/* Create the register check tasks, as described at the top of this file */\r
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
that they are all still running, and that none have detected an error. */\r
if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
{\r
-//_RB_ ulErrorFound = pdTRUE;\r
+ ulErrorFound = pdTRUE;\r
}\r
\r
if( xAreMathsTaskStillRunning() != pdTRUE )\r
\r
static void prvPseudoRandomiser( void *pvParameters )\r
{\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ), ulIBit = ( 1UL << 7UL );\r
volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
\r
+ /* A few minor port tests before entering the randomiser loop.\r
+\r
+ At this point interrupts should be enabled. */\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
+ /* The CPU does not have an interrupt mask register, so critical sections\r
+ have to globally disable interrupts. Therefore entering a critical section\r
+ should leave the I bit set. */\r
+ taskENTER_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* Nest the critical sections. */\r
+ taskENTER_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* After yielding the I bit should still be set. Note yielding is possible\r
+ in a critical section as each task maintains its own critical section\r
+ nesting count so some tasks are in critical sections and others are not -\r
+ however this is *not* something task code should do! */\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* The I bit should not be cleared again until both critical sections have\r
+ been exited. */\r
+ taskEXIT_CRITICAL();\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+ taskEXIT_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
/* This task does nothing other than ensure there is a little bit of\r
disruption in the scheduling pattern of the other tasks. Normally this is\r
done by generating interrupts at pseudo random times. */\r
projects / freertos / blobdiff