* ----------------------------------------------------------------------------\r
*/\r
\r
-/** \addtogroup ddrd_module \r
+/** \addtogroup ddrd_module\r
*\r
* The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises\r
* four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved\r
* to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.\r
- * \r
+ *\r
* \section ddr2 Configures DDR2\r
*\r
* The DDR2-SDRAM devices are initialized by the following sequence:\r
* <li> Step 1. Program the memory device type into the Memory Device Register</li>\r
* <li> Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.</li>\r
* <li> Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.</li>\r
- * <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must \r
- * set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command. \r
+ * <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must\r
+ * set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command.\r
* Now the clock which drives SDR-SDRAM device is enabled.</li>\r
* <li> Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the\r
* Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.</li>\r
/*@{*/\r
/*@}*/\r
\r
- \r
- \r
+\r
+\r
/**\r
* \file\r
*\r
*\r
*/\r
\r
- \r
+\r
/*----------------------------------------------------------------------------\r
* Headers\r
*----------------------------------------------------------------------------*/\r
*/\r
void BOARD_ConfigureVddMemSel( uint8_t VddMemSel )\r
{\r
+ ( void ) VddMemSel;\r
}\r
- \r
+\r
#define DDR2_BA0(r) (1 << (26 + r))\r
#define DDR2_BA1(r) (1 << (27 + r))\r
\r
static void matrix_configure_slave_ddr(void)\r
{\r
int ddr_port;\r
- \r
+\r
/* Disable write protection */\r
MATRIX0->MATRIX_WPMR = MPDDRC_WPMR_WPKEY_PASSWD;\r
- \r
+\r
/* Partition internal SRAM */\r
MATRIX0->MATRIX_SSR[11] = 0;\r
MATRIX0->MATRIX_SRTSR[11] = 0x05;\r
MATRIX0->MATRIX_SASSR[11] = 0x04;\r
- \r
+\r
ddr_port = 1;\r
- \r
+\r
/* Partition external DDR */\r
/* DDR port 0 not used from NWd */\r
for (ddr_port = 1 ; ddr_port < 8 ; ddr_port++) {\r
Refresh count: 8K\r
Row address: A[12:0] (8K)\r
Column address A[9:0] (1K)\r
- Bank address BA[2:0] a(24,25) (8) \r
+ Bank address BA[2:0] a(24,25) (8)\r
*/\r
void BOARD_ConfigureDdram( void )\r
{\r
volatile uint32_t i;\r
\r
volatile uint32_t dummy_value;\r
- \r
+\r
matrix_configure_slave_ddr();\r
\r
/* Enable DDR2 clock x2 in PMC */\r
PMC->PMC_PCER0 = (1 << (ID_MPDDRC));\r
PMC->PMC_SCER |= PMC_SCER_DDRCK;\r
- \r
+\r
/* MPDDRC I/O Calibration Register */\r
dummy_value = MPDDRC->MPDDRC_IO_CALIBR;\r
dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;\r
/* Step 1: Program the memory device type */\r
/* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/\r
\r
- MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM | MPDDRC_MD_DBW_DBW_32_BITS; \r
+ MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM | MPDDRC_MD_DBW_DBW_32_BITS;\r
\r
MPDDRC->MPDDRC_RD_DATA_PATH = MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE;\r
\r
MPDDRC_CR_NB_8_BANKS |\r
MPDDRC_CR_NDQS_DISABLED |\r
MPDDRC_CR_UNAL_SUPPORTED |\r
- MPDDRC_CR_OCD_DDR2_EXITCALIB; \r
- \r
+ MPDDRC_CR_OCD_DDR2_EXITCALIB;\r
+\r
MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(8) // 40 ns\r
| MPDDRC_TPR0_TRCD(3) // 12.5 ns\r
| MPDDRC_TPR0_TWR(3) // 15 ns\r
| MPDDRC_TPR0_TRRD(2) // 8 ns\r
| MPDDRC_TPR0_TWTR(2) // 2 clock cycle\r
| MPDDRC_TPR0_TMRD(2); // 2 clock cycles\r
- \r
+\r
\r
MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(23)\r
| MPDDRC_TPR1_TXSNR(25)\r
| MPDDRC_TPR1_TXSRD(200)\r
| MPDDRC_TPR1_TXP(2);\r
\r
- MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8) \r
+ MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8)\r
| MPDDRC_TPR2_TXARDS(2)\r
| MPDDRC_TPR2_TRPA(3)\r
| MPDDRC_TPR2_TRTP(2)\r
/* DDRSDRC Low-power Register */\r
for (i = 0; i < 13300; i++) {\r
asm("nop");\r
- } \r
+ }\r
\r
/* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into\r
the Mode Register, the application must set MODE to 1 in the Mode Register. */\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;\r
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command */\r
*pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/\r
- \r
+\r
/* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */\r
for (i = 0; i < 13300; i++) {\r
asm("nop");\r
- } \r
- \r
+ }\r
+\r
/* Step 4: An NOP command is issued to the DDR2-SDRAM */\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;\r
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/\r
for (i = 0; i < 100; i++) {\r
asm("nop");\r
}\r
- \r
+\r
/* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;\r
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/\r
for (i = 0; i < 100; i++) {\r
asm("nop");\r
}\r
- \r
+\r
/* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;\r
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */\r
}\r
\r
/* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */\r
- MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED; \r
+ MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED;\r
\r
/* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;\r
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;\r
*(pDdr) = 0;\r
\r
-/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. \r
+/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.\r
With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */\r
/* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average\r
- refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly \r
+ refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly\r
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */\r
/* ((64 x 10(^-3))/8192) x133 x (10^6) */\r
MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(0x2b0); /* Set Refresh timer 7.8125 us*/\r
HSMC->HSMC_CS_NUMBER[3].HSMC_MODE = HSMC_MODE_READ_MODE |\r
HSMC_MODE_WRITE_MODE |\r
((busWidth == 8 )? HSMC_MODE_DBW_BIT_8 :HSMC_MODE_DBW_BIT_16) |\r
- HSMC_MODE_TDF_CYCLES(1); \r
+ HSMC_MODE_TDF_CYCLES(1);\r
}\r
\r
\r
{\r
uint32_t dbw;\r
PMC_EnablePeripheral(ID_HSMC);\r
- if (busWidth == 8) \r
+ if (busWidth == 8)\r
{\r
dbw = HSMC_MODE_DBW_BIT_8;\r
}\r
projects / freertos / blobdiff