Core kernel files:

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D4x_EK_IAR / AtmelFiles / libchip_sama5d4x / include / icm.h

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libchip_sama5d4x/include/icm.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libchip_sama5d4x/include/icm.h
new file mode 100644 (file)
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+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/AtmelFiles/libchip_sama5d4x/include/icm.h
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------\r
+ *         SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _ICM_\r
+#define _ICM_\r
+\r
+/*------------------------------------------------------------------------------\r
+ *         Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/*         Definition                                                           */\r
+/*------------------------------------------------------------------------------*/\r
+#define ICM_RCFG_CDWBN (0x1u << 0) /**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */\r
+#define ICM_RCFG_WRAP (0x1u << 1) /**< \brief (ICM_RCFG) Wrap Command */\r
+#define ICM_RCFG_EOM (0x1u << 2) /**< \brief (ICM_RCFG) End Of Monitoring */\r
+#define ICM_RCFG_RHIEN (0x1u << 4) /**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */\r
+#define ICM_RCFG_DMIEN (0x1u << 5) /**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */\r
+#define ICM_RCFG_BEIEN (0x1u << 6) /**< \brief (ICM_RCFG) Bus error interrupt enable  */\r
+#define ICM_RCFG_WCIEN (0x1u << 7) /**< \brief (ICM_RCFG) Warp condition interrupt enable  */\r
+#define ICM_RCFG_ECIEN (0x1u << 8) /**< \brief (ICM_RCFG) End bit condition interrupt enable  */\r
+#define ICM_RCFG_SUIEN (0x1u << 9) /**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable  */\r
+#define ICM_RCFG_PROCDLY (0x1u << 10) /**< \brief (ICM_RCFG) Processing Delay*/\r
+#define ICM_RCFG_UALGO_Pos 12\r
+#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) /**< \brief (ICM_RCFG) User SHA Algorithm */\r
+#define   ICM_RCFG_ALGO_SHA1 (0x0u << 12) /**< \brief (ICM_RCFG) SHA1 algorithm processed */\r
+#define   ICM_RCFG_ALGO_SHA256 (0x1u << 12) /**< \brief (ICM_RCFG) SHA256 algorithm processed */\r
+#define   ICM_RCFG_ALGO_SHA224 (0x4u << 12) /**< \brief (ICM_RCFG) SHA224 algorithm processed */\r
+#define ICM_RCFG_MRPROT_Pos 24\r
+#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) /**< \brief (ICM_RCFG) Memory Region AHB Protection */\r
+#define ICM_RCFG_MRPROT(value) ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos)))\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/*         Type                                                                 */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/** \brief Structure ICM region descriptor area. */\r
+typedef struct _LinkedListDescriporIcmRegion\r
+{\r
+    /** the first byte address of the Region. */\r
+    uint32_t icm_raddr;\r
+    /** Configuration Structure Member. */\r
+    uint32_t icm_rcfg;\r
+    /** Control Structure Member. */\r
+    uint32_t icm_rctrl;\r
+    /** Next Address Structure Member. */\r
+    uint32_t icm_rnext;\r
+}LinkedListDescriporIcmRegion;\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/*         Exported functions                                                   */\r
+/*------------------------------------------------------------------------------*/\r
+extern void ICM_Enable(void);\r
+extern void ICM_Disable(void);\r
+extern void ICM_SoftReset(void);\r
+extern void ICM_ReComputeHash(uint8_t region);\r
+extern void ICM_EnableMonitor(uint8_t region);\r
+extern void ICM_DisableMonitor(uint8_t region);\r
+extern void ICM_Configure(uint32_t mode);\r
+extern void ICM_EnableIt(uint32_t sources);\r
+extern void ICM_DisableIt(uint32_t sources);\r
+extern uint32_t ICM_GetIntStatus(void);\r
+extern uint32_t ICM_GetStatus(void);\r
+extern uint32_t ICM_GetUStatus(void);\r
+extern void ICM_SetDescStartAddress(uint32_t addr);\r
+extern void ICM_SetHashStartAddress(uint32_t addr);\r
+extern void ICM_SetInitHashValue(uint32_t val);\r
+#endif /* #ifndef _ICM_ */\r