--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ IAR startup file for SAMA5D4X microcontrollers.\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION FIQ_STACK:DATA:NOROOT(2)\r
+ SECTION UND_STACK:DATA:NOROOT(2)\r
+ SECTION ABT_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#define __ASSEMBLY__\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#define AIC 0xFC06E000\r
+#define AIC_IVR 0x10\r
+#define AIC_EOICR 0x38\r
+#define L2CC_CR 0x00A00100\r
+\r
+#define REG_SFR_AICREDIR 0xF8028054\r
+#define REG_SFR_UID 0xF8028050\r
+#define AICREDIR_KEY 0x5F67B102\r
+\r
+\r
+MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_SYS 0x1F\r
+#define ARM_MODE_UND 0x1B\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+/*\r
+ Exception vectors\r
+ */\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetVector\r
+ PUBLIC IRQ_Handler\r
+ EXTERN FreeRTOS_IRQ_Handler\r
+ EXTERN Undefined_C_Handler\r
+ EXTERN FreeRTOS_SWI_Handler\r
+ EXTERN Prefetch_C_Handler\r
+ EXTERN Abort_C_Handler\r
+ PUBLIC FIQ_Handler\r
+\r
+ ARM\r
+\r
+__iar_init$$done: ; The interrupt vector is not needed\r
+ ; until after copy initialization is done\r
+\r
+resetVector:\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR pc, =resetHandler ; Reset\r
+ LDR pc, Undefined_Addr ; Undefined instructions\r
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)\r
+ LDR pc, Prefetch_Addr ; Prefetch abort\r
+ LDR pc, Abort_Addr ; Data abort\r
+ B . ; RESERVED\r
+ LDR PC,IRQ_Addr ; 0x18 IRQ\r
+ LDR PC,FIQ_Addr ; 0x1c FIQ\r
+\r
+IRQ_Addr: DCD FreeRTOS_IRQ_Handler\r
+Undefined_Addr: DCD Undefined_C_Handler\r
+SWI_Addr: DCD FreeRTOS_SWI_Handler\r
+Abort_Addr: DCD Abort_C_Handler\r
+Prefetch_Addr: DCD Prefetch_C_Handler\r
+;IRQ_Addr: DCD IRQ_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+/*\r
+ Handles incoming interrupt requests by branching to the corresponding\r
+ handler, as defined in the AIC. Supports interrupt nesting.\r
+ */\r
+IRQ_Handler:\r
+ /* Save interrupt context on the stack to allow nesting */\r
+ SUB lr, lr, #4\r
+ STMFD sp!, {lr}\r
+ MRS lr, SPSR\r
+ STMFD sp!, {r0, lr}\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+ LDR lr, =AIC\r
+ LDR r0, [r14, #AIC_IVR]\r
+ STR lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+ MSR CPSR_c, #ARM_MODE_SVC\r
+ STMFD sp!, {r1-r3, r4, r12, lr}\r
+\r
+ /* Check for 8-byte alignment and save lr plus a */\r
+ /* word to indicate the stack adjustment used (0 or 4) */\r
+ AND r1, sp, #4\r
+ SUB sp, sp, r1\r
+ STMFD sp!, {r1, lr}\r
+\r
+ BLX r0\r
+\r
+ LDMIA sp!, {r1, lr}\r
+ ADD sp, sp, r1\r
+\r
+ LDMIA sp!, {r1-r3, r4, r12, lr}\r
+ MSR CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+ LDR lr, =AIC\r
+ STR lr, [r14, #AIC_EOICR]\r
+\r
+ /* Restore interrupt context and branch back to calling code */\r
+ LDMIA sp!, {r0, lr}\r
+ MSR SPSR_cxsf, lr\r
+ LDMIA sp!, {pc}^\r
+\r
+\r
+/*\r
+ After a reset, execution starts here, the mode is ARM, supervisor\r
+ with interrupts disabled.\r
+ Initializes the chip and branches to the main() function.\r
+ */\r
+ SECTION .cstartup:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetHandler\r
+ EXTERN LowLevelInit\r
+ EXTERN ?main\r
+ REQUIRE resetVector\r
+ EXTERN CP15_InvalidateBTB\r
+ EXTERN CP15_InvalidateTranslationTable\r
+ EXTERN CP15_InvalidateIcache\r
+ EXTERN CP15_InvalidateDcacheBySetWay\r
+ ARM\r
+\r
+resetHandler:\r
+\r
+ LDR r4, =SFE(CSTACK) ; End of SVC stack\r
+ BIC r4,r4,#0x7 ; Make sure SP is 8 aligned\r
+ MOV sp, r4\r
+\r
+\r
+ ;; Set up the normal interrupt stack pointer.\r
+\r
+ MSR CPSR_c, #(ARM_MODE_IRQ | F_BIT | I_BIT)\r
+ LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+\r
+ ;; Set up the fast interrupt stack pointer.\r
+\r
+ MSR CPSR_c, #(ARM_MODE_FIQ | F_BIT | I_BIT)\r
+ LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ MSR CPSR_c, #(ARM_MODE_ABT | F_BIT | I_BIT)\r
+ LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ MSR CPSR_c, #(ARM_MODE_UND | F_BIT | I_BIT)\r
+ LDR sp, =SFE(UND_STACK) ; End of UND_STACK\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+ MSR CPSR_c, #(ARM_MODE_SYS | F_BIT | I_BIT)\r
+ LDR sp, =SFE(CSTACK-0x3000) ; 0x1000 bytes of SYS stack\r
+ BIC sp,sp,#0x7 ; Make sure SP is 8 aligned\r
+\r
+\r
+ MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)\r
+\r
+ CPSIE A\r
+\r
+ /* Enable VFP */\r
+ /* - Enable access to CP10 and CP11 in CP15.CACR */\r
+ MRC p15, 0, r0, c1, c0, 2\r
+ ORR r0, r0, #0xf00000\r
+ MCR p15, 0, r0, c1, c0, 2\r
+ /* - Enable access to CP10 and CP11 in CP15.NSACR */\r
+ /* - Set FPEXC.EN (B30) */\r
+#ifdef __ARMVFP__\r
+ MOV r3, #0x40000000\r
+ VMSR FPEXC, r3\r
+#endif\r
+\r
+ // Redirect FIQ to IRQ\r
+ LDR r0, =AICREDIR_KEY\r
+ LDR r1, = REG_SFR_UID\r
+ LDR r2, = REG_SFR_AICREDIR\r
+ LDR r3,[r1]\r
+ EORS r0, r0, r3\r
+ ORRS r0, r0, #0x01\r
+ STR r0, [r2]\r
+\r
+ /* Perform low-level initialization of the chip using LowLevelInit() */\r
+ LDR r0, =LowLevelInit\r
+ BLX r0\r
+\r
+\r
+ MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Regsiter into r0\r
+ TST r0, #0x1 ; Is the MMU enabled?\r
+ BICNE r0, r0, #0x1 ; Clear bit 0\r
+ TST r0, #0x4 ; Is the Dcache enabled?\r
+ BICNE r0, r0, #0x4 ; Clear bit 2\r
+ MCRNE p15, 0, r0, c1, c0, 0 ; Write value back\r
+\r
+ // Disbale L2 cache\r
+ LDR r1,=L2CC_CR\r
+ MOV r2,#0\r
+ STR r2, [r1]\r
+\r
+ DMB\r
+ BL CP15_InvalidateTranslationTable\r
+ BL CP15_InvalidateBTB\r
+ BL CP15_InvalidateIcache\r
+ BL CP15_InvalidateDcacheBySetWay\r
+ DMB\r
+ ISB\r
+\r
+\r
+ /* Branch to main() */\r
+ LDR r0, =?main\r
+ BLX r0\r
+\r
+ /* Loop indefinitely when program is finished */\r
+loop4:\r
+ B loop4\r
+\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+;- Function : FIQ_Handler\r
+;- Treatments : FIQ Controller Interrupt Handler.\r
+;- Called Functions : AIC_IVR[interrupt]\r
+;------------------------------------------------------------------------------\r
+SAIC DEFINE 0xFC068400\r
+AIC_FVR DEFINE 0x14\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ ARM\r
+FIQ_Handler:\r
+ /* Save interrupt context on the stack to allow nesting */\r
+ SUB lr, lr, #4\r
+ STMFD sp!, {lr}\r
+ /* MRS lr, SPSR */\r
+ STMFD sp!, {r0}\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+ LDR lr, =SAIC\r
+ LDR r0, [r14, #AIC_IVR]\r
+ STR lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+ MSR CPSR_c, #ARM_MODE_SVC\r
+ STMFD sp!, {r1-r3, r4, r12, lr}\r
+\r
+ MOV r14, pc\r
+ BX r0\r
+\r
+ LDMIA sp!, {r1-r3, r4, r12, lr}\r
+ MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+ LDR lr, =SAIC\r
+ STR lr, [r14, #AIC_EOICR]\r
+\r
+ /* Restore interrupt context and branch back to calling code */\r
+ LDMIA sp!, {r0}\r
+ /* MSR SPSR_cxsf, lr */\r
+ LDMIA sp!, {pc}^\r
+\r
+\r
+ END\r
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