Core kernel code:

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D4x_EK_IAR / cstartup_with_FreeRTOS_vectors.s

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/cstartup_with_FreeRTOS_vectors.s b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/cstartup_with_FreeRTOS_vectors.s
index 56dbb27905f84fa61b24ce6bc614259b5bab80dc..9625186426308e5f61eb88af5530a8a01cfbd8cf 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/cstartup_with_FreeRTOS_vectors.s
+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D4x_EK_IAR/cstartup_with_FreeRTOS_vectors.s
@@ -44,7 +44,6 @@
 //         Headers\r
 //------------------------------------------------------------------------------\r
 \r
-#define __ASSEMBLY__\r
 \r
 //------------------------------------------------------------------------------\r
 //         Definitions\r
@@ -82,7 +81,6 @@ MODE_MSK DEFINE 0x1F            ; Bit mask for mode bits in CPSR
         SECTION .vectors:CODE:NOROOT(2)\r
 \r
         PUBLIC  resetVector\r
-        PUBLIC  IRQ_Handler\r
         EXTERN  FreeRTOS_IRQ_Handler\r
         EXTERN  Undefined_C_Handler\r
         EXTERN  FreeRTOS_SWI_Handler\r
@@ -113,50 +111,7 @@ Undefined_Addr: DCD   Undefined_C_Handler
 SWI_Addr:       DCD   FreeRTOS_SWI_Handler\r
 Abort_Addr:     DCD   Abort_C_Handler\r
 Prefetch_Addr:  DCD   Prefetch_C_Handler\r
-;IRQ_Addr:       DCD   IRQ_Handler\r
 FIQ_Addr:       DCD   FIQ_Handler\r
-/*\r
-   Handles incoming interrupt requests by branching to the corresponding\r
-   handler, as defined in the AIC. Supports interrupt nesting.\r
- */\r
-IRQ_Handler:\r
-        /* Save interrupt context on the stack to allow nesting */\r
-        SUB     lr, lr, #4\r
-        STMFD   sp!, {lr}\r
-        MRS     lr, SPSR\r
-        STMFD   sp!, {r0, lr}\r
-\r
-        /* Write in the IVR to support Protect Mode */\r
-        LDR     lr, =AIC\r
-        LDR     r0, [r14, #AIC_IVR]\r
-        STR     lr, [r14, #AIC_IVR]\r
-\r
-        /* Branch to interrupt handler in Supervisor mode */\r
-        MSR     CPSR_c, #ARM_MODE_SVC\r
-        STMFD   sp!, {r1-r3, r4, r12, lr}\r
-\r
-        /* Check for 8-byte alignment and save lr plus a */\r
-        /* word to indicate the stack adjustment used (0 or 4) */\r
-        AND     r1, sp, #4\r
-        SUB     sp, sp, r1\r
-        STMFD   sp!, {r1, lr}\r
-\r
-        BLX     r0\r
-\r
-        LDMIA   sp!, {r1, lr}\r
-        ADD     sp, sp, r1\r
-\r
-        LDMIA   sp!, {r1-r3, r4, r12, lr}\r
-        MSR     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
-\r
-        /* Acknowledge interrupt */\r
-        LDR     lr, =AIC\r
-        STR     lr, [r14, #AIC_EOICR]\r
-\r
-        /* Restore interrupt context and branch back to calling code */\r
-        LDMIA   sp!, {r0, lr}\r
-        MSR     SPSR_cxsf, lr\r
-        LDMIA   sp!, {pc}^\r
 \r
 \r
 /*\r