--- /dev/null
+/******************************************************************************\r
+ *\r
+ * Copyright 2013 Altera Corporation. All Rights Reserved.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * \r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * \r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO\r
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ * \r
+ ******************************************************************************/\r
+\r
+#ifndef __ALT_DMA_COMMON_H__\r
+#define __ALT_DMA_COMMON_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif /* __cplusplus */\r
+\r
+/*!\r
+ * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions\r
+ *\r
+ * This module contains the common definitions for the DMA controller related\r
+ * APIs.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * This type definition enumerates the DMA controller channel threads.\r
+ */\r
+typedef enum ALT_DMA_CHANNEL_e\r
+{\r
+ ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */\r
+ ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */\r
+ ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */\r
+ ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */\r
+ ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */\r
+ ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */\r
+ ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */\r
+ ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */\r
+}\r
+ALT_DMA_CHANNEL_t;\r
+\r
+/*!\r
+ * This type definition enumerates the SoC system peripherals implementing the\r
+ * required request interface that enables direct DMA transfers to/from the\r
+ * device.\r
+ *\r
+ * FPGA soft IP interface to the DMA are required to comply with the Synopsys\r
+ * protocol.\r
+ *\r
+ * Request interface numbers 4 through 7 are multiplexed between the CAN\r
+ * controllers and soft logic implemented in the FPGA fabric. The selection\r
+ * between the CAN controller and FPGA interfaces is determined at DMA\r
+ * initialization.\r
+ */\r
+typedef enum ALT_DMA_PERIPH_e\r
+{\r
+ ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */\r
+ ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */\r
+ ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */\r
+ ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */\r
+\r
+ ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */\r
+ ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */\r
+ ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */\r
+ ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */\r
+\r
+ ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */\r
+ ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */\r
+ ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */\r
+ ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */\r
+\r
+ ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */\r
+ ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */\r
+ ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */\r
+ ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */\r
+\r
+ ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I<sup>2</sup>C 0 TX */\r
+ ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I<sup>2</sup>C 0 RX */\r
+ ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I<sup>2</sup>C 1 TX */\r
+ ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I<sup>2</sup>C 1 RX */\r
+ ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I<sup>2</sup>C 2 TX */\r
+ ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I<sup>2</sup>C 2 RX */\r
+ ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I<sup>2</sup>C 3 TX */\r
+ ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I<sup>2</sup>C 3 RX */\r
+ ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */\r
+ ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */\r
+ ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */\r
+ ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */\r
+ ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */\r
+ ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */\r
+ ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */\r
+ ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */\r
+ ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */\r
+ ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */\r
+ ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */\r
+ ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */\r
+ ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */\r
+ ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */\r
+ ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */\r
+ ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */\r
+}\r
+ALT_DMA_PERIPH_t;\r
+\r
+/*!\r
+ * This type enumerates the DMA security state options available.\r
+ */\r
+typedef enum ALT_DMA_SECURITY_e\r
+{\r
+ ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */\r
+ ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */\r
+ ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */\r
+}\r
+ALT_DMA_SECURITY_t;\r
+\r
+/*!\r
+ * This type definition enumerates the DMA event-interrupt resources.\r
+ */\r
+typedef enum ALT_DMA_EVENT_e\r
+{\r
+ ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */\r
+ ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */\r
+ ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */\r
+ ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */\r
+ ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */\r
+ ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */\r
+ ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */\r
+ ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */\r
+ ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */\r
+}\r
+ALT_DMA_EVENT_t;\r
+\r
+/*!\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __ALT_DMA_COMMON_H__ */\r
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