--- /dev/null
+/*******************************************************************************\r
+* *\r
+* Copyright 2013 Altera Corporation. All Rights Reserved. *\r
+* *\r
+* Redistribution and use in source and binary forms, with or without *\r
+* modification, are permitted provided that the following conditions are met: *\r
+* *\r
+* 1. Redistributions of source code must retain the above copyright notice, *\r
+* this list of conditions and the following disclaimer. *\r
+* *\r
+* 2. Redistributions in binary form must reproduce the above copyright notice, *\r
+* this list of conditions and the following disclaimer in the documentation *\r
+* and/or other materials provided with the distribution. *\r
+* *\r
+* 3. The name of the author may not be used to endorse or promote products *\r
+* derived from this software without specific prior written permission. *\r
+* *\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *\r
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *\r
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *\r
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *\r
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *\r
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *\r
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *\r
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *\r
+* *\r
+*******************************************************************************/\r
+\r
+/* Altera - ALT_F2H */\r
+\r
+#ifndef __ALTERA_ALT_F2H_H__\r
+#define __ALTERA_ALT_F2H_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif /* __cplusplus */\r
+\r
+/*\r
+ * Component : FPGA2HPS AXI Bridge Module - ALT_F2H\r
+ * FPGA2HPS AXI Bridge Module\r
+ * \r
+ * Registers in the FPGA2HPS AXI Bridge Module.\r
+ * \r
+ */\r
+/*\r
+ * Register Group : ID Register Group - ALT_F2H_IDGRP\r
+ * ID Register Group\r
+ * \r
+ * Contains registers that identify the ARM NIC-301 IP Core.\r
+ * \r
+ */\r
+/*\r
+ * Register : Peripheral ID4 Register - periph_id_4\r
+ * \r
+ * JEP106 continuation code\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:---------------\r
+ * [7:0] | R | 0x4 | Peripheral ID4\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Peripheral ID4 - periph_id_4\r
+ * \r
+ * JEP106 continuation code\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_PERIPH_ID_4.\r
+ */\r
+struct ALT_F2H_ID_PERIPH_ID_4_s\r
+{\r
+ const uint32_t periph_id_4 : 8; /* Peripheral ID4 */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_4. */\r
+typedef volatile struct ALT_F2H_ID_PERIPH_ID_4_s ALT_F2H_ID_PERIPH_ID_4_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_PERIPH_ID_4 register from the beginning of the component. */\r
+#define ALT_F2H_ID_PERIPH_ID_4_OFST 0xfd0\r
+\r
+/*\r
+ * Register : Peripheral ID0 Register - periph_id_0\r
+ * \r
+ * Peripheral ID0\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:------------------\r
+ * [7:0] | R | 0x1 | Part Number [7:0]\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Part Number [7:0] - pn7to0\r
+ * \r
+ * Part Number [7:0]\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_RESET 0x1\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_0_PN7TO0 field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_PERIPH_ID_0.\r
+ */\r
+struct ALT_F2H_ID_PERIPH_ID_0_s\r
+{\r
+ const uint32_t pn7to0 : 8; /* Part Number [7:0] */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_0. */\r
+typedef volatile struct ALT_F2H_ID_PERIPH_ID_0_s ALT_F2H_ID_PERIPH_ID_0_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_PERIPH_ID_0 register from the beginning of the component. */\r
+#define ALT_F2H_ID_PERIPH_ID_0_OFST 0xfe0\r
+\r
+/*\r
+ * Register : Peripheral ID1 Register - periph_id_1\r
+ * \r
+ * Peripheral ID1\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------------------\r
+ * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8]\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8\r
+ * \r
+ * JEP106[3:0], Part Number [11:8]\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_PERIPH_ID_1.\r
+ */\r
+struct ALT_F2H_ID_PERIPH_ID_1_s\r
+{\r
+ const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_1. */\r
+typedef volatile struct ALT_F2H_ID_PERIPH_ID_1_s ALT_F2H_ID_PERIPH_ID_1_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_PERIPH_ID_1 register from the beginning of the component. */\r
+#define ALT_F2H_ID_PERIPH_ID_1_OFST 0xfe4\r
+\r
+/*\r
+ * Register : Peripheral ID2 Register - periph_id_2\r
+ * \r
+ * Peripheral ID2\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:----------------------------------------\r
+ * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4]\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4\r
+ * \r
+ * Revision, JEP106 code flag, JEP106[6:4]\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_PERIPH_ID_2.\r
+ */\r
+struct ALT_F2H_ID_PERIPH_ID_2_s\r
+{\r
+ const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_2. */\r
+typedef volatile struct ALT_F2H_ID_PERIPH_ID_2_s ALT_F2H_ID_PERIPH_ID_2_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_PERIPH_ID_2 register from the beginning of the component. */\r
+#define ALT_F2H_ID_PERIPH_ID_2_OFST 0xfe8\r
+\r
+/*\r
+ * Register : Peripheral ID3 Register - periph_id_3\r
+ * \r
+ * Peripheral ID3\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:----------------------\r
+ * [3:0] | R | 0x0 | Customer Model Number\r
+ * [7:4] | R | 0x0 | Revision \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Customer Model Number - cust_mod_num\r
+ * \r
+ * Customer Model Number\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+/*\r
+ * Field : Revision - rev_and\r
+ * \r
+ * Revision\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_WIDTH 4\r
+/* The mask used to set the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0\r
+/* The mask used to clear the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f\r
+/* The reset value of the ALT_F2H_ID_PERIPH_ID_3_REV_AND register field. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_RESET 0x0\r
+/* Extracts the ALT_F2H_ID_PERIPH_ID_3_REV_AND field value from a register. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4)\r
+/* Produces a ALT_F2H_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_PERIPH_ID_3.\r
+ */\r
+struct ALT_F2H_ID_PERIPH_ID_3_s\r
+{\r
+ const uint32_t cust_mod_num : 4; /* Customer Model Number */\r
+ const uint32_t rev_and : 4; /* Revision */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_PERIPH_ID_3. */\r
+typedef volatile struct ALT_F2H_ID_PERIPH_ID_3_s ALT_F2H_ID_PERIPH_ID_3_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_PERIPH_ID_3 register from the beginning of the component. */\r
+#define ALT_F2H_ID_PERIPH_ID_3_OFST 0xfec\r
+\r
+/*\r
+ * Register : Component ID0 Register - comp_id_0\r
+ * \r
+ * Component ID0\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description\r
+ * :-------|:-------|:------|:------------\r
+ * [7:0] | R | 0xd | Preamble \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Preamble - preamble\r
+ * \r
+ * Preamble\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_COMP_ID_0_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_RESET 0xd\r
+/* Extracts the ALT_F2H_ID_COMP_ID_0_PREAMBLE field value from a register. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_COMP_ID_0.\r
+ */\r
+struct ALT_F2H_ID_COMP_ID_0_s\r
+{\r
+ const uint32_t preamble : 8; /* Preamble */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_COMP_ID_0. */\r
+typedef volatile struct ALT_F2H_ID_COMP_ID_0_s ALT_F2H_ID_COMP_ID_0_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_COMP_ID_0 register from the beginning of the component. */\r
+#define ALT_F2H_ID_COMP_ID_0_OFST 0xff0\r
+\r
+/*\r
+ * Register : Component ID1 Register - comp_id_1\r
+ * \r
+ * Component ID1\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------------------------------\r
+ * [7:0] | R | 0xf0 | Generic IP component class, Preamble\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Generic IP component class, Preamble - genipcompcls_preamble\r
+ * \r
+ * Generic IP component class, Preamble\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0\r
+/* Extracts the ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_COMP_ID_1.\r
+ */\r
+struct ALT_F2H_ID_COMP_ID_1_s\r
+{\r
+ const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_COMP_ID_1. */\r
+typedef volatile struct ALT_F2H_ID_COMP_ID_1_s ALT_F2H_ID_COMP_ID_1_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_COMP_ID_1 register from the beginning of the component. */\r
+#define ALT_F2H_ID_COMP_ID_1_OFST 0xff4\r
+\r
+/*\r
+ * Register : Component ID2 Register - comp_id_2\r
+ * \r
+ * Component ID2\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description\r
+ * :-------|:-------|:------|:------------\r
+ * [7:0] | R | 0x5 | Preamble \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Preamble - preamble\r
+ * \r
+ * Preamble\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_COMP_ID_2_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_RESET 0x5\r
+/* Extracts the ALT_F2H_ID_COMP_ID_2_PREAMBLE field value from a register. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_COMP_ID_2.\r
+ */\r
+struct ALT_F2H_ID_COMP_ID_2_s\r
+{\r
+ const uint32_t preamble : 8; /* Preamble */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_COMP_ID_2. */\r
+typedef volatile struct ALT_F2H_ID_COMP_ID_2_s ALT_F2H_ID_COMP_ID_2_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_COMP_ID_2 register from the beginning of the component. */\r
+#define ALT_F2H_ID_COMP_ID_2_OFST 0xff8\r
+\r
+/*\r
+ * Register : Component ID3 Register - comp_id_3\r
+ * \r
+ * Component ID3\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description\r
+ * :-------|:-------|:------|:------------\r
+ * [7:0] | R | 0xb1 | Preamble \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Preamble - preamble\r
+ * \r
+ * Preamble\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_MSB 7\r
+/* The width in bits of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_WIDTH 8\r
+/* The mask used to set the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_F2H_ID_COMP_ID_3_PREAMBLE register field. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_RESET 0xb1\r
+/* Extracts the ALT_F2H_ID_COMP_ID_3_PREAMBLE field value from a register. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_F2H_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */\r
+#define ALT_F2H_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_ID_COMP_ID_3.\r
+ */\r
+struct ALT_F2H_ID_COMP_ID_3_s\r
+{\r
+ const uint32_t preamble : 8; /* Preamble */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_ID_COMP_ID_3. */\r
+typedef volatile struct ALT_F2H_ID_COMP_ID_3_s ALT_F2H_ID_COMP_ID_3_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_ID_COMP_ID_3 register from the beginning of the component. */\r
+#define ALT_F2H_ID_COMP_ID_3_OFST 0xffc\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_F2H_IDGRP.\r
+ */\r
+struct ALT_F2H_IDGRP_s\r
+{\r
+ volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_ID_PERIPH_ID_4_t periph_id_4; /* ALT_F2H_ID_PERIPH_ID_4 */\r
+ volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_ID_PERIPH_ID_0_t periph_id_0; /* ALT_F2H_ID_PERIPH_ID_0 */\r
+ volatile ALT_F2H_ID_PERIPH_ID_1_t periph_id_1; /* ALT_F2H_ID_PERIPH_ID_1 */\r
+ volatile ALT_F2H_ID_PERIPH_ID_2_t periph_id_2; /* ALT_F2H_ID_PERIPH_ID_2 */\r
+ volatile ALT_F2H_ID_PERIPH_ID_3_t periph_id_3; /* ALT_F2H_ID_PERIPH_ID_3 */\r
+ volatile ALT_F2H_ID_COMP_ID_0_t comp_id_0; /* ALT_F2H_ID_COMP_ID_0 */\r
+ volatile ALT_F2H_ID_COMP_ID_1_t comp_id_1; /* ALT_F2H_ID_COMP_ID_1 */\r
+ volatile ALT_F2H_ID_COMP_ID_2_t comp_id_2; /* ALT_F2H_ID_COMP_ID_2 */\r
+ volatile ALT_F2H_ID_COMP_ID_3_t comp_id_3; /* ALT_F2H_ID_COMP_ID_3 */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_F2H_IDGRP. */\r
+typedef volatile struct ALT_F2H_IDGRP_s ALT_F2H_IDGRP_t;\r
+/* The struct declaration for the raw register contents of register group ALT_F2H_IDGRP. */\r
+struct ALT_F2H_IDGRP_raw_s\r
+{\r
+ volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */\r
+ volatile uint32_t periph_id_4; /* ALT_F2H_ID_PERIPH_ID_4 */\r
+ volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */\r
+ volatile uint32_t periph_id_0; /* ALT_F2H_ID_PERIPH_ID_0 */\r
+ volatile uint32_t periph_id_1; /* ALT_F2H_ID_PERIPH_ID_1 */\r
+ volatile uint32_t periph_id_2; /* ALT_F2H_ID_PERIPH_ID_2 */\r
+ volatile uint32_t periph_id_3; /* ALT_F2H_ID_PERIPH_ID_3 */\r
+ volatile uint32_t comp_id_0; /* ALT_F2H_ID_COMP_ID_0 */\r
+ volatile uint32_t comp_id_1; /* ALT_F2H_ID_COMP_ID_1 */\r
+ volatile uint32_t comp_id_2; /* ALT_F2H_ID_COMP_ID_2 */\r
+ volatile uint32_t comp_id_3; /* ALT_F2H_ID_COMP_ID_3 */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_F2H_IDGRP. */\r
+typedef volatile struct ALT_F2H_IDGRP_raw_s ALT_F2H_IDGRP_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+/*\r
+ * Register Group : Slave Register Group - ALT_F2H_SLVGRP\r
+ * Slave Register Group\r
+ * \r
+ * Registers associated with slave interfaces.\r
+ * \r
+ */\r
+/*\r
+ * Register Group : 32-bit Slave - ALT_F2H_SLV_B32\r
+ * 32-bit Slave\r
+ * \r
+ * Registers associated with the 32-bit AXI slave interface.\r
+ * \r
+ * These registers are only active when the FPGA2HPS AXI Bridge is configured with\r
+ * a 32-bit FPGA AXI slave interface.\r
+ * \r
+ */\r
+/*\r
+ * Register : Functionality Modification 2 Register - fn_mod2\r
+ * \r
+ * Controls bypass merge of upsizing/downsizing.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------\r
+ * [0] | RW | 0x0 | Bypass Merge\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Bypass Merge - bypass_merge\r
+ * \r
+ * Controls bypass merge of upsizing/downsizing.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------------------|:------|:-------------------------------------------------\r
+ * ALT_F2H_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. \r
+ * ALT_F2H_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that\r
+ * : | | could pass through the upsizer legally without \r
+ * : | | alteration. \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD2_BYPASS_MERGE\r
+ * \r
+ * The network can alter transactions.\r
+ */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD2_BYPASS_MERGE\r
+ * \r
+ * The network does not alter any transactions that could pass through the upsizer\r
+ * legally without alteration.\r
+ */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_MSB 0\r
+/* The width in bits of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_WIDTH 1\r
+/* The mask used to set the ALT_F2H_FN_MOD2_BYPASS_MERGE register field value. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_F2H_FN_MOD2_BYPASS_MERGE register field value. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_F2H_FN_MOD2_BYPASS_MERGE register field. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_RESET 0x0\r
+/* Extracts the ALT_F2H_FN_MOD2_BYPASS_MERGE field value from a register. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_F2H_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */\r
+#define ALT_F2H_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_FN_MOD2.\r
+ */\r
+struct ALT_F2H_FN_MOD2_s\r
+{\r
+ uint32_t bypass_merge : 1; /* Bypass Merge */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_FN_MOD2. */\r
+typedef volatile struct ALT_F2H_FN_MOD2_s ALT_F2H_FN_MOD2_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_FN_MOD2 register from the beginning of the component. */\r
+#define ALT_F2H_FN_MOD2_OFST 0x24\r
+/* The address of the ALT_F2H_FN_MOD2 register. */\r
+#define ALT_F2H_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_F2H_FN_MOD2_OFST))\r
+\r
+/*\r
+ * Register : Issuing Functionality Modification Register - fn_mod\r
+ * \r
+ * Sets the block issuing capability to multiple or single outstanding\r
+ * transactions.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:------------------\r
+ * [0] | RW | 0x0 | ALT_F2H_FN_MOD_RD\r
+ * [1] | RW | 0x0 | ALT_F2H_FN_MOD_WR\r
+ * [31:2] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : rd\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:-------------------------------------------\r
+ * ALT_F2H_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions \r
+ * ALT_F2H_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD_RD\r
+ * \r
+ * Multiple outstanding read transactions\r
+ */\r
+#define ALT_F2H_FN_MOD_RD_E_MULT 0x0\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD_RD\r
+ * \r
+ * Only a single outstanding read transaction\r
+ */\r
+#define ALT_F2H_FN_MOD_RD_E_SINGLE 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD_RD register field. */\r
+#define ALT_F2H_FN_MOD_RD_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD_RD register field. */\r
+#define ALT_F2H_FN_MOD_RD_MSB 0\r
+/* The width in bits of the ALT_F2H_FN_MOD_RD register field. */\r
+#define ALT_F2H_FN_MOD_RD_WIDTH 1\r
+/* The mask used to set the ALT_F2H_FN_MOD_RD register field value. */\r
+#define ALT_F2H_FN_MOD_RD_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_F2H_FN_MOD_RD register field value. */\r
+#define ALT_F2H_FN_MOD_RD_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_F2H_FN_MOD_RD register field. */\r
+#define ALT_F2H_FN_MOD_RD_RESET 0x0\r
+/* Extracts the ALT_F2H_FN_MOD_RD field value from a register. */\r
+#define ALT_F2H_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_F2H_FN_MOD_RD register field value suitable for setting the register. */\r
+#define ALT_F2H_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : wr\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:--------------------------------------------\r
+ * ALT_F2H_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions \r
+ * ALT_F2H_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD_WR\r
+ * \r
+ * Multiple outstanding write transactions\r
+ */\r
+#define ALT_F2H_FN_MOD_WR_E_MULT 0x0\r
+/*\r
+ * Enumerated value for register field ALT_F2H_FN_MOD_WR\r
+ * \r
+ * Only a single outstanding write transaction\r
+ */\r
+#define ALT_F2H_FN_MOD_WR_E_SINGLE 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_F2H_FN_MOD_WR register field. */\r
+#define ALT_F2H_FN_MOD_WR_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_F2H_FN_MOD_WR register field. */\r
+#define ALT_F2H_FN_MOD_WR_MSB 1\r
+/* The width in bits of the ALT_F2H_FN_MOD_WR register field. */\r
+#define ALT_F2H_FN_MOD_WR_WIDTH 1\r
+/* The mask used to set the ALT_F2H_FN_MOD_WR register field value. */\r
+#define ALT_F2H_FN_MOD_WR_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_F2H_FN_MOD_WR register field value. */\r
+#define ALT_F2H_FN_MOD_WR_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_F2H_FN_MOD_WR register field. */\r
+#define ALT_F2H_FN_MOD_WR_RESET 0x0\r
+/* Extracts the ALT_F2H_FN_MOD_WR field value from a register. */\r
+#define ALT_F2H_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_F2H_FN_MOD_WR register field value suitable for setting the register. */\r
+#define ALT_F2H_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_F2H_FN_MOD.\r
+ */\r
+struct ALT_F2H_FN_MOD_s\r
+{\r
+ uint32_t rd : 1; /* ALT_F2H_FN_MOD_RD */\r
+ uint32_t wr : 1; /* ALT_F2H_FN_MOD_WR */\r
+ uint32_t : 30; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_F2H_FN_MOD. */\r
+typedef volatile struct ALT_F2H_FN_MOD_s ALT_F2H_FN_MOD_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_F2H_FN_MOD register from the beginning of the component. */\r
+#define ALT_F2H_FN_MOD_OFST 0x108\r
+/* The address of the ALT_F2H_FN_MOD register. */\r
+#define ALT_F2H_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_F2H_FN_MOD_OFST))\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_F2H_SLV_B32.\r
+ */\r
+struct ALT_F2H_SLV_B32_s\r
+{\r
+ volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_FN_MOD2_t fn_mod2; /* ALT_F2H_FN_MOD2 */\r
+ volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_FN_MOD_t fn_mod; /* ALT_F2H_FN_MOD */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_F2H_SLV_B32. */\r
+typedef volatile struct ALT_F2H_SLV_B32_s ALT_F2H_SLV_B32_t;\r
+/* The struct declaration for the raw register contents of register group ALT_F2H_SLV_B32. */\r
+struct ALT_F2H_SLV_B32_raw_s\r
+{\r
+ volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */\r
+ volatile uint32_t fn_mod2; /* ALT_F2H_FN_MOD2 */\r
+ volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */\r
+ volatile uint32_t fn_mod; /* ALT_F2H_FN_MOD */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_F2H_SLV_B32. */\r
+typedef volatile struct ALT_F2H_SLV_B32_raw_s ALT_F2H_SLV_B32_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+/*\r
+ * Register Group : 128-bit Slave - ALT_F2H_SLV_B128\r
+ * 128-bit Slave\r
+ * \r
+ * Registers associated with the 128-bit AXI slave interface.\r
+ * \r
+ * These registers are only active when the FPGA2HPS AXI Bridge is configured with\r
+ * a 128-bit FPGA AXI slave interface.\r
+ * \r
+ */\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_F2H_SLV_B128.\r
+ */\r
+struct ALT_F2H_SLV_B128_s\r
+{\r
+ volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_FN_MOD2_t fn_mod2; /* ALT_F2H_FN_MOD2 */\r
+ volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_FN_MOD_t fn_mod; /* ALT_F2H_FN_MOD */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_F2H_SLV_B128. */\r
+typedef volatile struct ALT_F2H_SLV_B128_s ALT_F2H_SLV_B128_t;\r
+/* The struct declaration for the raw register contents of register group ALT_F2H_SLV_B128. */\r
+struct ALT_F2H_SLV_B128_raw_s\r
+{\r
+ volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */\r
+ volatile uint32_t fn_mod2; /* ALT_F2H_FN_MOD2 */\r
+ volatile uint32_t _pad_0x28_0x107[56]; /* *UNDEFINED* */\r
+ volatile uint32_t fn_mod; /* ALT_F2H_FN_MOD */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_F2H_SLV_B128. */\r
+typedef volatile struct ALT_F2H_SLV_B128_raw_s ALT_F2H_SLV_B128_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_F2H_SLVGRP.\r
+ */\r
+struct ALT_F2H_SLVGRP_s\r
+{\r
+ volatile ALT_F2H_SLV_B32_t slavegrp_b32; /* ALT_F2H_SLV_B32 */\r
+ volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_SLV_B128_t slavegrp_b128; /* ALT_F2H_SLV_B128 */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_F2H_SLVGRP. */\r
+typedef volatile struct ALT_F2H_SLVGRP_s ALT_F2H_SLVGRP_t;\r
+/* The struct declaration for the raw register contents of register group ALT_F2H_SLVGRP. */\r
+struct ALT_F2H_SLVGRP_raw_s\r
+{\r
+ volatile ALT_F2H_SLV_B32_raw_t slavegrp_b32; /* ALT_F2H_SLV_B32 */\r
+ volatile uint32_t _pad_0x10c_0x1fff[1981]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_SLV_B128_raw_t slavegrp_b128; /* ALT_F2H_SLV_B128 */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_F2H_SLVGRP. */\r
+typedef volatile struct ALT_F2H_SLVGRP_raw_s ALT_F2H_SLVGRP_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_F2H.\r
+ */\r
+struct ALT_F2H_s\r
+{\r
+ volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_IDGRP_t idgrp; /* ALT_F2H_IDGRP */\r
+ volatile uint32_t _pad_0x2000_0x41fff[65536]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_SLVGRP_t slavegrp; /* ALT_F2H_SLVGRP */\r
+ volatile uint32_t _pad_0x4410c_0x80000[61373]; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_F2H. */\r
+typedef volatile struct ALT_F2H_s ALT_F2H_t;\r
+/* The struct declaration for the raw register contents of register group ALT_F2H. */\r
+struct ALT_F2H_raw_s\r
+{\r
+ volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_IDGRP_raw_t idgrp; /* ALT_F2H_IDGRP */\r
+ volatile uint32_t _pad_0x2000_0x41fff[65536]; /* *UNDEFINED* */\r
+ volatile ALT_F2H_SLVGRP_raw_t slavegrp; /* ALT_F2H_SLVGRP */\r
+ volatile uint32_t _pad_0x4410c_0x80000[61373]; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_F2H. */\r
+typedef volatile struct ALT_F2H_raw_s ALT_F2H_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+#endif /* __ALTERA_ALT_F2H_H__ */\r
+\r
projects / freertos / blobdiff