--- /dev/null
+/*******************************************************************************\r
+* *\r
+* Copyright 2013 Altera Corporation. All Rights Reserved. *\r
+* *\r
+* Redistribution and use in source and binary forms, with or without *\r
+* modification, are permitted provided that the following conditions are met: *\r
+* *\r
+* 1. Redistributions of source code must retain the above copyright notice, *\r
+* this list of conditions and the following disclaimer. *\r
+* *\r
+* 2. Redistributions in binary form must reproduce the above copyright notice, *\r
+* this list of conditions and the following disclaimer in the documentation *\r
+* and/or other materials provided with the distribution. *\r
+* *\r
+* 3. The name of the author may not be used to endorse or promote products *\r
+* derived from this software without specific prior written permission. *\r
+* *\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *\r
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *\r
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *\r
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *\r
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *\r
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *\r
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *\r
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *\r
+* *\r
+*******************************************************************************/\r
+\r
+/* Altera - ALT_FPGAMGRDATA */\r
+\r
+#ifndef __ALTERA_ALT_FPGAMGRDATA_H__\r
+#define __ALTERA_ALT_FPGAMGRDATA_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif /* __cplusplus */\r
+\r
+/*\r
+ * Component : FPGA Manager Module Configuration Data - ALT_FPGAMGRDATA\r
+ * FPGA Manager Module Configuration Data\r
+ * \r
+ * Registers in the FPGA Manager module accessible via its AXI slave\r
+ * \r
+ */\r
+/*\r
+ * Register : Write Data Register - data\r
+ * \r
+ * Used to send configuration image to FPGA.\r
+ * \r
+ * The DATA register accepts 4 bytes of the configuration image on each write. The\r
+ * configuration image byte-stream is converted into a 4-byte word with little-\r
+ * endian ordering. If the configuration image is not an integer multiple of 4\r
+ * bytes, software should pad the configuration image with extra zero bytes to make\r
+ * it an integer multiple of 4 bytes.\r
+ * \r
+ * The FPGA Manager converts the DATA to 16 bits wide when writing CB.DATA for\r
+ * partial reconfiguration.\r
+ * \r
+ * The FPGA Manager waits to transmit the data to the CB until the FPGA is able to\r
+ * receive it. For a full configuration, the FPGA Manager waits until the FPGA\r
+ * exits the Reset Phase and enters the Configuration Phase. For a partial\r
+ * reconfiguration, the FPGA Manager waits until the CB.PR_READY signal indicates\r
+ * that the FPGA is ready.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:--------|:-----------------\r
+ * [31:0] | RW | Unknown | Write Data Value\r
+ * \r
+ */\r
+/*\r
+ * Field : Write Data Value - value\r
+ * \r
+ * Accepts configuration image to be sent to CB when the HPS configures the FPGA.\r
+ * Software normally just writes this register. If software reads this register, it\r
+ * returns the value 0 and replies with an AXI SLVERR error.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_FPGAMGRDATA_DATA_VALUE register field. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_MSB 31\r
+/* The width in bits of the ALT_FPGAMGRDATA_DATA_VALUE register field. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_WIDTH 32\r
+/* The mask used to set the ALT_FPGAMGRDATA_DATA_VALUE register field value. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_SET_MSK 0xffffffff\r
+/* The mask used to clear the ALT_FPGAMGRDATA_DATA_VALUE register field value. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_CLR_MSK 0x00000000\r
+/* The reset value of the ALT_FPGAMGRDATA_DATA_VALUE register field is UNKNOWN. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_RESET 0x0\r
+/* Extracts the ALT_FPGAMGRDATA_DATA_VALUE field value from a register. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_FPGAMGRDATA_DATA_VALUE register field value suitable for setting the register. */\r
+#define ALT_FPGAMGRDATA_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_FPGAMGRDATA_DATA.\r
+ */\r
+struct ALT_FPGAMGRDATA_DATA_s\r
+{\r
+ uint32_t value : 32; /* Write Data Value */\r
+};\r
+\r
+/* The typedef declaration for register ALT_FPGAMGRDATA_DATA. */\r
+typedef volatile struct ALT_FPGAMGRDATA_DATA_s ALT_FPGAMGRDATA_DATA_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_FPGAMGRDATA_DATA register from the beginning of the component. */\r
+#define ALT_FPGAMGRDATA_DATA_OFST 0x0\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_FPGAMGRDATA.\r
+ */\r
+struct ALT_FPGAMGRDATA_s\r
+{\r
+ volatile ALT_FPGAMGRDATA_DATA_t data; /* ALT_FPGAMGRDATA_DATA */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_FPGAMGRDATA. */\r
+typedef volatile struct ALT_FPGAMGRDATA_s ALT_FPGAMGRDATA_t;\r
+/* The struct declaration for the raw register contents of register group ALT_FPGAMGRDATA. */\r
+struct ALT_FPGAMGRDATA_raw_s\r
+{\r
+ volatile uint32_t data; /* ALT_FPGAMGRDATA_DATA */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_FPGAMGRDATA. */\r
+typedef volatile struct ALT_FPGAMGRDATA_raw_s ALT_FPGAMGRDATA_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+#endif /* __ALTERA_ALT_FPGAMGRDATA_H__ */\r
+\r
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