Added project for Altera Cyclone V SoC, currently running from internal RAM.

[freertos] / FreeRTOS / Demo / CORTEX_A9_Cyclone_V_SoC_DK / Altera_Code / HardwareLibrary / include / socal / alt_sdr.h

diff --git a/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h
new file mode 100644 (file)
index 0000000..62ad5b2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/HardwareLibrary/include/socal/alt_sdr.h
@@ -0,0 +1,4149 @@
+/*******************************************************************************\r
+*                                                                              *\r
+* Copyright 2013 Altera Corporation. All Rights Reserved.                      *\r
+*                                                                              *\r
+* Redistribution and use in source and binary forms, with or without           *\r
+* modification, are permitted provided that the following conditions are met:  *\r
+*                                                                              *\r
+* 1. Redistributions of source code must retain the above copyright notice,    *\r
+*    this list of conditions and the following disclaimer.                     *\r
+*                                                                              *\r
+* 2. Redistributions in binary form must reproduce the above copyright notice, *\r
+*    this list of conditions and the following disclaimer in the documentation *\r
+*    and/or other materials provided with the distribution.                    *\r
+*                                                                              *\r
+* 3. The name of the author may not be used to endorse or promote products     *\r
+*    derived from this software without specific prior written permission.     *\r
+*                                                                              *\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *\r
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *\r
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *\r
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *\r
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *\r
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *\r
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *\r
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *\r
+*                                                                              *\r
+*******************************************************************************/\r
+\r
+/* Altera - ALT_SDR */\r
+\r
+#ifndef __ALTERA_ALT_SDR_H__\r
+#define __ALTERA_ALT_SDR_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif  /* __cplusplus */\r
+\r
+/*\r
+ * Component : SDRAM Controller - ALT_SDR\r
+ * SDRAM Controller\r
+ * \r
+ * Address map for the SDRAM Interface registers\r
+ * \r
+ */\r
+/*\r
+ * Register Group : SDRAM Controller Module - ALT_SDR_CTL\r
+ * SDRAM Controller Module\r
+ * \r
+ * Address map for the SDRAM controller and multi-port front-end.\r
+ * \r
+ * All registers in this group reset to zero.\r
+ * \r
+ */\r
+/*\r
+ * Register : Controller Configuration Register - ctrlcfg\r
+ * \r
+ * The Controller Configuration Register determines the behavior of the controller.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description               \r
+ * :--------|:-------|:--------|:---------------------------\r
+ *  [2:0]   | RW     | Unknown | DRAM Memory Type          \r
+ *  [7:3]   | RW     | Unknown | DRAM Memory Burst Length  \r
+ *  [9:8]   | RW     | Unknown | Address Interleaving Order\r
+ *  [10]    | RW     | Unknown | ECC Enable                \r
+ *  [11]    | RW     | Unknown | ECC Auto-Correction Enable\r
+ *  [12]    | RW     | Unknown | TBD                       \r
+ *  [13]    | RW     | Unknown | Generate Single Bit Errors\r
+ *  [14]    | RW     | Unknown | Generate Double Bit Errors\r
+ *  [15]    | RW     | Unknown | Command Reorder Enable    \r
+ *  [21:16] | RW     | Unknown | Starvation Limit          \r
+ *  [22]    | RW     | Unknown | DQS Tracking Enable       \r
+ *  [23]    | RW     | Unknown | No DM Pins Present        \r
+ *  [24]    | RW     | Unknown | Burst Interrupt Enable    \r
+ *  [25]    | RW     | Unknown | Burst Terminate Enable    \r
+ *  [31:26] | ???    | Unknown | *UNDEFINED*               \r
+ * \r
+ */\r
+/*\r
+ * Field : DRAM Memory Type - memtype\r
+ * \r
+ * Selects memory type. Program this field with one of the following binary values,\r
+ * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011"\r
+ * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH      3\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK    0x00000007\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK    0xfffffff8\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007)\r
+\r
+/*\r
+ * Field : DRAM Memory Burst Length - membl\r
+ * \r
+ * Configures burst length as a static decimal value.  Legal values are valid for\r
+ * JEDEC allowed DRAM values for the DRAM selected in cfg_type.  For DDR3, this\r
+ * should be programmed with 8 (binary &quot;01000&quot;), for DDR2 it can be\r
+ * either 4 or 8 depending on the exact DRAM chip.  LPDDR2 can be programmed with\r
+ * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program\r
+ * the membl field in the staticcfg register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK    0x000000f8\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK    0xffffff07\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8)\r
+\r
+/*\r
+ * Field : Address Interleaving Order - addrorder\r
+ * \r
+ * Selects the order for address interleaving.  Programming this field with\r
+ * different values gives different mappings between the AXI or Avalon-MM address\r
+ * and the SDRAM address. Program this field with the following binary values to\r
+ * select the ordering. &quot;00&quot; - chip, row, bank, column, &quot;01&quot; -\r
+ * chip, bank, row, column, &quot;10&quot;-row, chip, bank, column\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB        8\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB        9\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK    0x00000300\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK    0xfffffcff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300)\r
+\r
+/*\r
+ * Field : ECC Enable - eccen\r
+ * \r
+ * Enable the generation and checking of ECC.  This bit must only be set if the\r
+ * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this,\r
+ * you must clear the useeccasdata field in the staticcfg register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB        10\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB        10\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK    0x00000400\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK    0xfffffbff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400)\r
+\r
+/*\r
+ * Field : ECC Auto-Correction Enable - ecccorren\r
+ * \r
+ * Enable auto correction of the read data returned when single bit error is\r
+ * detected.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB        11\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB        11\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK    0x00000800\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK    0xfffff7ff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800)\r
+\r
+/*\r
+ * Field : TBD - cfg_enable_ecc_code_overwrites\r
+ * \r
+ * Set to a one to enable ECC overwrites.  ECC overwrites occur when a correctable\r
+ * ECC error is seen and cause a new read/modify/write to be scheduled for that\r
+ * location to clear the ECC error.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB        12\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB        12\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK    0x00001000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK    0xffffefff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000)\r
+\r
+/*\r
+ * Field : Generate Single Bit Errors - gensbe\r
+ * \r
+ * Enable the deliberate insertion of single bit errors in data written to memory.\r
+ * This should only be used for testing purposes.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB        13\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB        13\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK    0x00002000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK    0xffffdfff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000)\r
+\r
+/*\r
+ * Field : Generate Double Bit Errors - gendbe\r
+ * \r
+ * Enable the deliberate insertion of double bit errors in data written to memory.\r
+ * This should only be used for testing purposes.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB        14\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB        14\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK    0x00004000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK    0xffffbfff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000)\r
+\r
+/*\r
+ * Field : Command Reorder Enable - reorderen\r
+ * \r
+ * This bit controls whether the controller can re-order operations to optimize\r
+ * SDRAM bandwidth.  It should generally be set to a one.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB        15\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB        15\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK    0x00008000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK    0xffff7fff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000)\r
+\r
+/*\r
+ * Field : Starvation Limit - starvelimit\r
+ * \r
+ * Specifies the number of DRAM burst transactions an individual transaction will\r
+ * allow to reorder ahead of it before its priority is raised in the memory\r
+ * controller.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB        16\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB        21\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH      6\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK    0x003f0000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK    0xffc0ffff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000)\r
+\r
+/*\r
+ * Field : DQS Tracking Enable - dqstrken\r
+ * \r
+ * Enables DQS tracking in the PHY.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB        22\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB        22\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK    0x00400000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK    0xffbfffff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000)\r
+\r
+/*\r
+ * Field : No DM Pins Present - nodmpins\r
+ * \r
+ * Set to a one to enable DRAM operation if no DM pins are connected.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB        23\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB        23\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK    0x00800000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK    0xff7fffff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000)\r
+\r
+/*\r
+ * Field : Burst Interrupt Enable - burstintren\r
+ * \r
+ * Set to a one to enable the controller to issue burst interrupt commands. This\r
+ * must only be set when the DRAM memory type is LPDDR2.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB        24\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB        24\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK    0x01000000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK    0xfeffffff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000)\r
+\r
+/*\r
+ * Field : Burst Terminate Enable - bursttermen\r
+ * \r
+ * Set to a one to enable the controller to issue burst terminate commands. This\r
+ * must only be set when the DRAM memory type is LPDDR2.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB        25\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB        25\r
+/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK    0x02000000\r
+/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK    0xfdffffff\r
+/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25)\r
+/* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_CTLCFG.\r
+ */\r
+struct ALT_SDR_CTL_CTLCFG_s\r
+{\r
+    uint32_t  memtype                        :  3;  /* DRAM Memory Type */\r
+    uint32_t  membl                          :  5;  /* DRAM Memory Burst Length */\r
+    uint32_t  addrorder                      :  2;  /* Address Interleaving Order */\r
+    uint32_t  eccen                          :  1;  /* ECC Enable */\r
+    uint32_t  ecccorren                      :  1;  /* ECC Auto-Correction Enable */\r
+    uint32_t  cfg_enable_ecc_code_overwrites :  1;  /* TBD */\r
+    uint32_t  gensbe                         :  1;  /* Generate Single Bit Errors */\r
+    uint32_t  gendbe                         :  1;  /* Generate Double Bit Errors */\r
+    uint32_t  reorderen                      :  1;  /* Command Reorder Enable */\r
+    uint32_t  starvelimit                    :  6;  /* Starvation Limit */\r
+    uint32_t  dqstrken                       :  1;  /* DQS Tracking Enable */\r
+    uint32_t  nodmpins                       :  1;  /* No DM Pins Present */\r
+    uint32_t  burstintren                    :  1;  /* Burst Interrupt Enable */\r
+    uint32_t  bursttermen                    :  1;  /* Burst Terminate Enable */\r
+    uint32_t                                 :  6;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */\r
+typedef volatile struct ALT_SDR_CTL_CTLCFG_s  ALT_SDR_CTL_CTLCFG_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */\r
+#define ALT_SDR_CTL_CTLCFG_OFST        0x0\r
+\r
+/*\r
+ * Register : DRAM Timings 1 Register - dramtiming1\r
+ * \r
+ * This register implements JEDEC standardized timing parameters.  It should be\r
+ * programmed in clock cycles, for the value specified by the memory vendor.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description               \r
+ * :--------|:-------|:--------|:---------------------------\r
+ *  [3:0]   | RW     | Unknown | CAS Write Latency         \r
+ *  [8:4]   | RW     | Unknown | Additive Latency          \r
+ *  [13:9]  | RW     | Unknown | CAS Read Latency          \r
+ *  [17:14] | RW     | Unknown | Activate to Activate Delay\r
+ *  [23:18] | RW     | Unknown | Four Activate Window Time \r
+ *  [31:24] | RW     | Unknown | Refresh Cycle Time        \r
+ * \r
+ */\r
+/*\r
+ * Field : CAS Write Latency - tcwl\r
+ * \r
+ * Memory write latency.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK    0x0000000f\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK    0xfffffff0\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+/*\r
+ * Field : Additive Latency - tal\r
+ * \r
+ * Memory additive latency.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB        8\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK    0x000001f0\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK    0xfffffe0f\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0)\r
+\r
+/*\r
+ * Field : CAS Read Latency - tcl\r
+ * \r
+ * Memory read latency.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB        9\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB        13\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK    0x00003e00\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK    0xffffc1ff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00)\r
+\r
+/*\r
+ * Field : Activate to Activate Delay - trrd\r
+ * \r
+ * The activate to activate, different banks timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB        14\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB        17\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK    0x0003c000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK    0xfffc3fff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000)\r
+\r
+/*\r
+ * Field : Four Activate Window Time - tfaw\r
+ * \r
+ * The four-activate window timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB        18\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB        23\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH      6\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK    0x00fc0000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK    0xff03ffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000)\r
+\r
+/*\r
+ * Field : Refresh Cycle Time - trfc\r
+ * \r
+ * The refresh cycle timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB        24\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK    0xff000000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK    0x00ffffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1.\r
+ */\r
+struct ALT_SDR_CTL_DRAMTIMING1_s\r
+{\r
+    uint32_t  tcwl :  4;  /* CAS Write Latency */\r
+    uint32_t  tal  :  5;  /* Additive Latency */\r
+    uint32_t  tcl  :  5;  /* CAS Read Latency */\r
+    uint32_t  trrd :  4;  /* Activate to Activate Delay */\r
+    uint32_t  tfaw :  6;  /* Four Activate Window Time */\r
+    uint32_t  trfc :  8;  /* Refresh Cycle Time */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s  ALT_SDR_CTL_DRAMTIMING1_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMTIMING1_OFST        0x4\r
+\r
+/*\r
+ * Register : DRAM Timings 2 Register - dramtiming2\r
+ * \r
+ * This register implements JEDEC standardized timing parameters.  It should be\r
+ * programmed in clock cycles, for the value specified by the memory vendor.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description                    \r
+ * :--------|:-------|:--------|:--------------------------------\r
+ *  [12:0]  | RW     | Unknown | Refresh Interval               \r
+ *  [16:13] | RW     | Unknown | Activate to Read or Write Delay\r
+ *  [20:17] | RW     | Unknown | Row Precharge Time             \r
+ *  [24:21] | RW     | Unknown | Write Recovery Time            \r
+ *  [28:25] | RW     | Unknown | Write to Read Time             \r
+ *  [31:29] | ???    | 0x0     | *UNDEFINED*                    \r
+ * \r
+ */\r
+/*\r
+ * Field : Refresh Interval - trefi\r
+ * \r
+ * The refresh interval timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB        12\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH      13\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK    0x00001fff\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK    0xffffe000\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff)\r
+\r
+/*\r
+ * Field : Activate to Read or Write Delay - trcd\r
+ * \r
+ * The activate to read/write timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB        13\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB        16\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK    0x0001e000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK    0xfffe1fff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000)\r
+\r
+/*\r
+ * Field : Row Precharge Time - trp\r
+ * \r
+ * The precharge to activate timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB        17\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB        20\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK    0x001e0000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK    0xffe1ffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000)\r
+\r
+/*\r
+ * Field : Write Recovery Time - twr\r
+ * \r
+ * The write recovery timing.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB        21\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB        24\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK    0x01e00000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK    0xfe1fffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000)\r
+\r
+/*\r
+ * Field : Write to Read Time - twtr\r
+ * \r
+ * The write to read timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB        25\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB        28\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK    0x1e000000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK    0xe1ffffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2.\r
+ */\r
+struct ALT_SDR_CTL_DRAMTIMING2_s\r
+{\r
+    uint32_t  trefi : 13;  /* Refresh Interval */\r
+    uint32_t  trcd  :  4;  /* Activate to Read or Write Delay */\r
+    uint32_t  trp   :  4;  /* Row Precharge Time */\r
+    uint32_t  twr   :  4;  /* Write Recovery Time */\r
+    uint32_t  twtr  :  4;  /* Write to Read Time */\r
+    uint32_t        :  3;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s  ALT_SDR_CTL_DRAMTIMING2_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMTIMING2_OFST        0x8\r
+\r
+/*\r
+ * Register : DRAM Timings 3 Register - dramtiming3\r
+ * \r
+ * This register implements JEDEC standardized timing parameters.  It should be\r
+ * programmed in clock cycles, for the value specified by the memory vendor.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description                    \r
+ * :--------|:-------|:--------|:--------------------------------\r
+ *  [3:0]   | RW     | Unknown | Read to Precharge Time         \r
+ *  [8:4]   | RW     | Unknown | Activate to Precharge Time     \r
+ *  [14:9]  | RW     | Unknown | Row Cycle Time                 \r
+ *  [18:15] | RW     | Unknown | Mode Register Programming Delay\r
+ *  [22:19] | RW     | Unknown | CAS to CAS Delay               \r
+ *  [31:23] | ???    | 0x0     | *UNDEFINED*                    \r
+ * \r
+ */\r
+/*\r
+ * Field : Read to Precharge Time - trtp\r
+ * \r
+ * The read to precharge timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK    0x0000000f\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK    0xfffffff0\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+/*\r
+ * Field : Activate to Precharge Time - tras\r
+ * \r
+ * The activate to precharge timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB        8\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK    0x000001f0\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK    0xfffffe0f\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0)\r
+\r
+/*\r
+ * Field : Row Cycle Time - trc\r
+ * \r
+ * The activate to activate timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB        9\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB        14\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH      6\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK    0x00007e00\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK    0xffff81ff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00)\r
+\r
+/*\r
+ * Field : Mode Register Programming Delay - tmrd\r
+ * \r
+ * Mode register timing parameter.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB        15\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB        18\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK    0x00078000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK    0xfff87fff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000)\r
+\r
+/*\r
+ * Field : CAS to CAS Delay - tccd\r
+ * \r
+ * The CAS to CAS delay time.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB        19\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB        22\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK    0x00780000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK    0xff87ffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3.\r
+ */\r
+struct ALT_SDR_CTL_DRAMTIMING3_s\r
+{\r
+    uint32_t  trtp :  4;  /* Read to Precharge Time */\r
+    uint32_t  tras :  5;  /* Activate to Precharge Time */\r
+    uint32_t  trc  :  6;  /* Row Cycle Time */\r
+    uint32_t  tmrd :  4;  /* Mode Register Programming Delay */\r
+    uint32_t  tccd :  4;  /* CAS to CAS Delay */\r
+    uint32_t       :  9;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s  ALT_SDR_CTL_DRAMTIMING3_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMTIMING3_OFST        0xc\r
+\r
+/*\r
+ * Register : DRAM Timings 4 Register - dramtiming4\r
+ * \r
+ * This register implements JEDEC standardized timing parameters.  It should be\r
+ * programmed in clock cycles, for the value specified by the memory vendor.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description                   \r
+ * :--------|:-------|:--------|:-------------------------------\r
+ *  [9:0]   | RW     | Unknown | Self-refresh Exit             \r
+ *  [19:10] | RW     | Unknown | Power Down Exit               \r
+ *  [23:20] | RW     | Unknown | Minimum Low Power State Cycles\r
+ *  [31:24] | ???    | 0x0     | *UNDEFINED*                   \r
+ * \r
+ */\r
+/*\r
+ * Field : Self-refresh Exit - selfrfshexit\r
+ * \r
+ * The self refresh exit cycles, tXS.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB        9\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK    0x000003ff\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK    0xfffffc00\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff)\r
+\r
+/*\r
+ * Field : Power Down Exit - pwrdownexit\r
+ * \r
+ * The power down exit cycles, tXPDLL.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB        10\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB        19\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK    0x000ffc00\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK    0xfff003ff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00)\r
+\r
+/*\r
+ * Field : Minimum Low Power State Cycles - minpwrsavecycles\r
+ * \r
+ * The minimum number of cycles to stay in a low power state. This applies to both\r
+ * power down and self-refresh and should be set to the greater of tPD and tCKESR.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB        20\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB        23\r
+/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK    0x00f00000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK    0xff0fffff\r
+/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20)\r
+/* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4.\r
+ */\r
+struct ALT_SDR_CTL_DRAMTIMING4_s\r
+{\r
+    uint32_t  selfrfshexit     : 10;  /* Self-refresh Exit */\r
+    uint32_t  pwrdownexit      : 10;  /* Power Down Exit */\r
+    uint32_t  minpwrsavecycles :  4;  /* Minimum Low Power State Cycles */\r
+    uint32_t                   :  8;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s  ALT_SDR_CTL_DRAMTIMING4_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMTIMING4_OFST        0x10\r
+\r
+/*\r
+ * Register : Lower Power Timing Register - lowpwrtiming\r
+ * \r
+ * This register controls the behavior of the low power logic in the controller.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description               \r
+ * :--------|:-------|:--------|:---------------------------\r
+ *  [15:0]  | RW     | Unknown | Auto-power Down Cycles    \r
+ *  [19:16] | RW     | Unknown | Clock Disable Delay Cycles\r
+ *  [31:20] | ???    | 0x0     | *UNDEFINED*               \r
+ * \r
+ */\r
+/*\r
+ * Field : Auto-power Down Cycles - autopdcycles\r
+ * \r
+ * The number of idle clock cycles after which the controller should place the\r
+ * memory into power-down mode.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB        15\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH      16\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK    0x0000ffff\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK    0xffff0000\r
+/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff)\r
+\r
+/*\r
+ * Field : Clock Disable Delay Cycles - clkdisablecycles\r
+ * \r
+ * Set to a the number of clocks after the execution of an self-refresh to stop the\r
+ * clock.  This register is generally set based on PHY design latency and should\r
+ * generally not be changed.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB        16\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB        19\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK    0x000f0000\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK    0xfff0ffff\r
+/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16)\r
+/* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING.\r
+ */\r
+struct ALT_SDR_CTL_LOWPWRTIMING_s\r
+{\r
+    uint32_t  autopdcycles     : 16;  /* Auto-power Down Cycles */\r
+    uint32_t  clkdisablecycles :  4;  /* Clock Disable Delay Cycles */\r
+    uint32_t                   : 12;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */\r
+typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s  ALT_SDR_CTL_LOWPWRTIMING_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */\r
+#define ALT_SDR_CTL_LOWPWRTIMING_OFST        0x14\r
+\r
+/*\r
+ * Register : ODT Control Register - dramodt\r
+ * \r
+ * This register controls which ODT pin is asserted during reads or writes. Bits\r
+ * [1:0] control which ODT pin is asserted during to accesses to chip select 0,\r
+ * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For\r
+ * example, a value of &quot;1001&quot; will cause ODT[0] to be asserted for\r
+ * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this\r
+ * to &quot;0001&quot; if there is only one chip select available.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description      \r
+ * :-------|:-------|:--------|:------------------\r
+ *  [3:0]  | RW     | Unknown | Write ODT Control\r
+ *  [7:4]  | RW     | Unknown | Read ODT Control \r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*      \r
+ * \r
+ */\r
+/*\r
+ * Field : Write ODT Control - cfg_write_odt_chip\r
+ * \r
+ * This register controls which ODT pin is asserted during writes.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK    0x0000000f\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK    0xfffffff0\r
+/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+/*\r
+ * Field : Read ODT Control - cfg_read_odt_chip\r
+ * \r
+ * This register controls which ODT pin is asserted during reads.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK    0x000000f0\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK    0xffffff0f\r
+/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4)\r
+/* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMODT.\r
+ */\r
+struct ALT_SDR_CTL_DRAMODT_s\r
+{\r
+    uint32_t  cfg_write_odt_chip :  4;  /* Write ODT Control */\r
+    uint32_t  cfg_read_odt_chip  :  4;  /* Read ODT Control */\r
+    uint32_t                     : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMODT_s  ALT_SDR_CTL_DRAMODT_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMODT_OFST        0x18\r
+\r
+/*\r
+ * Register : DRAM Address Widths Register - dramaddrw\r
+ * \r
+ * This register configures the width of the various address fields of the DRAM.\r
+ * The values specified in this register must match the memory devices being used.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description             \r
+ * :--------|:-------|:--------|:-------------------------\r
+ *  [4:0]   | RW     | Unknown | DRAM Column Address Bits\r
+ *  [9:5]   | RW     | Unknown | DRAM Row Address Bits   \r
+ *  [12:10] | RW     | Unknown | DRAM Bank Address Bits  \r
+ *  [15:13] | RW     | Unknown | DRAM Chip Address Bits  \r
+ *  [31:16] | ???    | 0x0     | *UNDEFINED*             \r
+ * \r
+ */\r
+/*\r
+ * Field : DRAM Column Address Bits - colbits\r
+ * \r
+ * The number of column address bits for the memory devices in your memory\r
+ * interface.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB        4\r
+/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK    0x0000001f\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK    0xffffffe0\r
+/* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f)\r
+\r
+/*\r
+ * Field : DRAM Row Address Bits - rowbits\r
+ * \r
+ * The number of row address bits for the memory devices in your memory interface.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB        5\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB        9\r
+/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK    0x000003e0\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK    0xfffffc1f\r
+/* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5)\r
+/* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0)\r
+\r
+/*\r
+ * Field : DRAM Bank Address Bits - bankbits\r
+ * \r
+ * The number of bank address bits for the memory devices in your memory interface.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB        10\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB        12\r
+/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH      3\r
+/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK    0x00001c00\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK    0xffffe3ff\r
+/* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10)\r
+/* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00)\r
+\r
+/*\r
+ * Field : DRAM Chip Address Bits - csbits\r
+ * \r
+ * The number of chip select address bits for the memory devices in your memory\r
+ * interface.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB        13\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB        15\r
+/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH      3\r
+/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK    0x0000e000\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK    0xffff1fff\r
+/* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13)\r
+/* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMADDRW.\r
+ */\r
+struct ALT_SDR_CTL_DRAMADDRW_s\r
+{\r
+    uint32_t  colbits  :  5;  /* DRAM Column Address Bits */\r
+    uint32_t  rowbits  :  5;  /* DRAM Row Address Bits */\r
+    uint32_t  bankbits :  3;  /* DRAM Bank Address Bits */\r
+    uint32_t  csbits   :  3;  /* DRAM Chip Address Bits */\r
+    uint32_t           : 16;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s  ALT_SDR_CTL_DRAMADDRW_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMADDRW_OFST        0x2c\r
+\r
+/*\r
+ * Register : DRAM Interface Data Width Register - dramifwidth\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description              \r
+ * :-------|:-------|:--------|:--------------------------\r
+ *  [7:0]  | RW     | Unknown | DRAM Interface Data Width\r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*              \r
+ * \r
+ */\r
+/*\r
+ * Field : DRAM Interface Data Width - ifwidth\r
+ * \r
+ * This register controls the interface width of the SDRAM interface, including any\r
+ * bits used for ECC. For example, for a 32-bit interface with ECC, program this\r
+ * register with 0x28. You must also program the ctrlwidth register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK    0x000000ff\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK    0xffffff00\r
+/* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH.\r
+ */\r
+struct ALT_SDR_CTL_DRAMIFWIDTH_s\r
+{\r
+    uint32_t  ifwidth :  8;  /* DRAM Interface Data Width */\r
+    uint32_t          : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s  ALT_SDR_CTL_DRAMIFWIDTH_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMIFWIDTH_OFST        0x30\r
+\r
+/*\r
+ * Register : DRAM Devices Data Width Register - dramdevwidth\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description            \r
+ * :-------|:-------|:--------|:------------------------\r
+ *  [3:0]  | RW     | Unknown | DRAM Devices Data Width\r
+ *  [31:4] | ???    | 0x0     | *UNDEFINED*            \r
+ * \r
+ */\r
+/*\r
+ * Field : DRAM Devices Data Width - devwidth\r
+ * \r
+ * This register specifies the width of the physical DRAM chips, for example 8 or\r
+ * 16.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH      4\r
+/* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK    0x0000000f\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK    0xfffffff0\r
+/* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH.\r
+ */\r
+struct ALT_SDR_CTL_DRAMDEVWIDTH_s\r
+{\r
+    uint32_t  devwidth :  4;  /* DRAM Devices Data Width */\r
+    uint32_t           : 28;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s  ALT_SDR_CTL_DRAMDEVWIDTH_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMDEVWIDTH_OFST        0x34\r
+\r
+/*\r
+ * Register : DRAM Status Register - dramsts\r
+ * \r
+ * This register provides the status of the calibration and ECC logic.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                \r
+ * :-------|:-------|:--------|:----------------------------\r
+ *  [0]    | RW     | Unknown | PHY Calibration Successful \r
+ *  [1]    | RW     | Unknown | PHY Calibration Failed     \r
+ *  [2]    | RW     | Unknown | Single Bit Error Seen      \r
+ *  [3]    | RW     | Unknown | Double Bit Error Seen      \r
+ *  [4]    | RW     | Unknown | ECC Auto-Correction Dropped\r
+ *  [31:5] | ???    | 0x0     | *UNDEFINED*                \r
+ * \r
+ */\r
+/*\r
+ * Field : PHY Calibration Successful - calsuccess\r
+ * \r
+ * This bit will be set to 1 if the PHY was able to successfully calibrate.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB        0\r
+/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK    0x00000001\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK    0xfffffffe\r
+/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : PHY Calibration Failed - calfail\r
+ * \r
+ * This bit  will be set to 1 if the PHY was unable to calibrate.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB        1\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK    0x00000002\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK    0xfffffffd\r
+/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Single Bit Error Seen - sbeerr\r
+ * \r
+ * This bit will be set to 1 if there have been any ECC single bit errors detected.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB        2\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK    0x00000004\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK    0xfffffffb\r
+/* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Double Bit Error Seen - dbeerr\r
+ * \r
+ * This bit will be set to 1 if there have been any ECC double bit errors detected.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK    0x00000008\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK    0xfffffff7\r
+/* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : ECC Auto-Correction Dropped - corrdrop\r
+ * \r
+ * This bit will be set to 1 if there any auto-corrections have been dropped.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB        4\r
+/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK    0x00000010\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK    0xffffffef\r
+/* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMSTS.\r
+ */\r
+struct ALT_SDR_CTL_DRAMSTS_s\r
+{\r
+    uint32_t  calsuccess :  1;  /* PHY Calibration Successful */\r
+    uint32_t  calfail    :  1;  /* PHY Calibration Failed */\r
+    uint32_t  sbeerr     :  1;  /* Single Bit Error Seen */\r
+    uint32_t  dbeerr     :  1;  /* Double Bit Error Seen */\r
+    uint32_t  corrdrop   :  1;  /* ECC Auto-Correction Dropped */\r
+    uint32_t             : 27;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMSTS_s  ALT_SDR_CTL_DRAMSTS_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMSTS_OFST        0x38\r
+\r
+/*\r
+ * Register : ECC Interrupt  Register - dramintr\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                           \r
+ * :-------|:-------|:--------|:---------------------------------------\r
+ *  [0]    | RW     | Unknown | Interrupt Enable                      \r
+ *  [1]    | RW     | Unknown | Mask Single Bit Error Interrupt       \r
+ *  [2]    | RW     | Unknown | Mask Double Bit Error Interrupt       \r
+ *  [3]    | RW     | Unknown | Mask Dropped Auto-correction Interrupt\r
+ *  [4]    | RW     | Unknown | Clear Interrupt Signal                \r
+ *  [31:5] | ???    | 0x0     | *UNDEFINED*                           \r
+ * \r
+ */\r
+/*\r
+ * Field : Interrupt Enable - intren\r
+ * \r
+ * Enable the interrupt output.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB        0\r
+/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK    0x00000001\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK    0xfffffffe\r
+/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Mask Single Bit Error Interrupt - sbemask\r
+ * \r
+ * Mask the single bit error interrupt.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB        1\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK    0x00000002\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK    0xfffffffd\r
+/* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Mask Double Bit Error Interrupt - dbemask\r
+ * \r
+ * Mask the double bit error interrupt.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB        2\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK    0x00000004\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK    0xfffffffb\r
+/* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Mask Dropped Auto-correction Interrupt - corrdropmask\r
+ * \r
+ * Set this bit to a one to mask interrupts for an ECC correction write back\r
+ * needing to be dropped.  This indicates a burst of memory errors in a short\r
+ * period of time.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK    0x00000008\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK    0xfffffff7\r
+/* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Clear Interrupt Signal - intrclr\r
+ * \r
+ * Writing to this self-clearing bit clears the interrupt signal. Writing to this\r
+ * bit also clears the error count and error address registers.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB        4\r
+/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK    0x00000010\r
+/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK    0xffffffef\r
+/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DRAMINTR.\r
+ */\r
+struct ALT_SDR_CTL_DRAMINTR_s\r
+{\r
+    uint32_t  intren       :  1;  /* Interrupt Enable */\r
+    uint32_t  sbemask      :  1;  /* Mask Single Bit Error Interrupt */\r
+    uint32_t  dbemask      :  1;  /* Mask Double Bit Error Interrupt */\r
+    uint32_t  corrdropmask :  1;  /* Mask Dropped Auto-correction Interrupt */\r
+    uint32_t  intrclr      :  1;  /* Clear Interrupt Signal */\r
+    uint32_t               : 27;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */\r
+typedef volatile struct ALT_SDR_CTL_DRAMINTR_s  ALT_SDR_CTL_DRAMINTR_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DRAMINTR_OFST        0x3c\r
+\r
+/*\r
+ * Register : ECC Single Bit Error Count Register - sbecount\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description           \r
+ * :-------|:-------|:--------|:-----------------------\r
+ *  [7:0]  | RW     | Unknown | Single Bit Error Count\r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*           \r
+ * \r
+ */\r
+/*\r
+ * Field : Single Bit Error Count - count\r
+ * \r
+ * Reports the number of single bit errors that have occurred since the status\r
+ * register counters were last cleared.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK    0x000000ff\r
+/* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK    0xffffff00\r
+/* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_SBECOUNT.\r
+ */\r
+struct ALT_SDR_CTL_SBECOUNT_s\r
+{\r
+    uint32_t  count :  8;  /* Single Bit Error Count */\r
+    uint32_t        : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */\r
+typedef volatile struct ALT_SDR_CTL_SBECOUNT_s  ALT_SDR_CTL_SBECOUNT_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */\r
+#define ALT_SDR_CTL_SBECOUNT_OFST        0x40\r
+\r
+/*\r
+ * Register : ECC Double Bit Error Count Register - dbecount\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description           \r
+ * :-------|:-------|:--------|:-----------------------\r
+ *  [7:0]  | RW     | Unknown | Double Bit Error Count\r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*           \r
+ * \r
+ */\r
+/*\r
+ * Field : Double Bit Error Count - count\r
+ * \r
+ * Reports the number of double bit errors that have occurred since the status\r
+ * register counters were last cleared.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK    0x000000ff\r
+/* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK    0xffffff00\r
+/* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DBECOUNT.\r
+ */\r
+struct ALT_SDR_CTL_DBECOUNT_s\r
+{\r
+    uint32_t  count :  8;  /* Double Bit Error Count */\r
+    uint32_t        : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */\r
+typedef volatile struct ALT_SDR_CTL_DBECOUNT_s  ALT_SDR_CTL_DBECOUNT_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DBECOUNT_OFST        0x44\r
+\r
+/*\r
+ * Register : ECC Error Address Register - erraddr\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description      \r
+ * :-------|:-------|:--------|:------------------\r
+ *  [31:0] | RW     | Unknown | ECC Error Address\r
+ * \r
+ */\r
+/*\r
+ * Field : ECC Error Address - addr\r
+ * \r
+ * The address of the most recent ECC error.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH      32\r
+/* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK    0xffffffff\r
+/* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK    0x00000000\r
+/* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_ERRADDR.\r
+ */\r
+struct ALT_SDR_CTL_ERRADDR_s\r
+{\r
+    uint32_t  addr : 32;  /* ECC Error Address */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */\r
+typedef volatile struct ALT_SDR_CTL_ERRADDR_s  ALT_SDR_CTL_ERRADDR_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */\r
+#define ALT_SDR_CTL_ERRADDR_OFST        0x48\r
+\r
+/*\r
+ * Register : ECC Auto-correction Dropped Count Register - dropcount\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                  \r
+ * :-------|:-------|:--------|:------------------------------\r
+ *  [7:0]  | RW     | Unknown | Dropped Auto-correction Count\r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*                  \r
+ * \r
+ */\r
+/*\r
+ * Field : Dropped Auto-correction Count - corrdropcount\r
+ * \r
+ * This gives the count of the number of ECC write back transactions dropped due to\r
+ * the internal FIFO overflowing.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK    0x000000ff\r
+/* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK    0xffffff00\r
+/* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DROPCOUNT.\r
+ */\r
+struct ALT_SDR_CTL_DROPCOUNT_s\r
+{\r
+    uint32_t  corrdropcount :  8;  /* Dropped Auto-correction Count */\r
+    uint32_t                : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */\r
+typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s  ALT_SDR_CTL_DROPCOUNT_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DROPCOUNT_OFST        0x4c\r
+\r
+/*\r
+ * Register : ECC Auto-correction Dropped Address Register - dropaddr\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                    \r
+ * :-------|:-------|:--------|:--------------------------------\r
+ *  [31:0] | RW     | Unknown | Dropped Auto-correction Address\r
+ * \r
+ */\r
+/*\r
+ * Field : Dropped Auto-correction Address - corrdropaddr\r
+ * \r
+ * This register gives the last address which was dropped.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH      32\r
+/* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK    0xffffffff\r
+/* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK    0x00000000\r
+/* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_DROPADDR.\r
+ */\r
+struct ALT_SDR_CTL_DROPADDR_s\r
+{\r
+    uint32_t  corrdropaddr : 32;  /* Dropped Auto-correction Address */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */\r
+typedef volatile struct ALT_SDR_CTL_DROPADDR_s  ALT_SDR_CTL_DROPADDR_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */\r
+#define ALT_SDR_CTL_DROPADDR_OFST        0x50\r
+\r
+/*\r
+ * Register : Low Power Control Register - lowpwreq\r
+ * \r
+ * This register instructs the controller to put the DRAM into a power down state.\r
+ * Note that some commands are only valid for certain memory types.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                     \r
+ * :-------|:-------|:--------|:---------------------------------\r
+ *  [0]    | RW     | Unknown | Deep Power Down Request         \r
+ *  [2:1]  | RW     | Unknown | Deep Power Down Chip Select Mask\r
+ *  [3]    | RW     | Unknown | Self-refresh Request            \r
+ *  [5:4]  | RW     | Unknown | Self-refresh Chip Select Mask   \r
+ *  [31:6] | ???    | 0x0     | *UNDEFINED*                     \r
+ * \r
+ */\r
+/*\r
+ * Field : Deep Power Down Request - deeppwrdnreq\r
+ * \r
+ * Write a one to this bit to request a deep power down.  This bit should only be\r
+ * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB        0\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK    0x00000001\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK    0xfffffffe\r
+/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Deep Power Down Chip Select Mask - deeppwrdnmask\r
+ * \r
+ * Write ones to this register to select which DRAM chip selects will be powered\r
+ * down.  Typical usage is to set both of these bits when deeppwrdnreq is set but\r
+ * the controller does support putting a single chip into deep power down and\r
+ * keeping the other chip running.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB        1\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK    0x00000006\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK    0xfffffff9\r
+/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1)\r
+/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006)\r
+\r
+/*\r
+ * Field : Self-refresh Request - selfrshreq\r
+ * \r
+ * Write a one to this bit to request the RAM be put into a self refresh state.\r
+ * This bit is treated as a static value so the RAM will remain in self-refresh as\r
+ * long as this register bit is set to a one.  This power down mode can be selected\r
+ * for all DRAMs supported by the controller.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK    0x00000008\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK    0xfffffff7\r
+/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Self-refresh Chip Select Mask - selfrfshmask\r
+ * \r
+ * Write a one to each bit of this field to have a self refresh request apply to\r
+ * both chips.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB        4\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB        5\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK    0x00000030\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK    0xffffffcf\r
+/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4)\r
+/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_LOWPWREQ.\r
+ */\r
+struct ALT_SDR_CTL_LOWPWREQ_s\r
+{\r
+    uint32_t  deeppwrdnreq  :  1;  /* Deep Power Down Request */\r
+    uint32_t  deeppwrdnmask :  2;  /* Deep Power Down Chip Select Mask */\r
+    uint32_t  selfrshreq    :  1;  /* Self-refresh Request */\r
+    uint32_t  selfrfshmask  :  2;  /* Self-refresh Chip Select Mask */\r
+    uint32_t                : 26;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */\r
+typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s  ALT_SDR_CTL_LOWPWREQ_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */\r
+#define ALT_SDR_CTL_LOWPWREQ_OFST        0x54\r
+\r
+/*\r
+ * Register : Low Power Acknowledge Register - lowpwrack\r
+ * \r
+ * This register gives the status of the power down commands requested by the Low\r
+ * Power Control register.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                \r
+ * :-------|:-------|:--------|:----------------------------\r
+ *  [0]    | RW     | Unknown | Deep Power Down Acknowledge\r
+ *  [1]    | RW     | Unknown | Self-refresh Acknowledge   \r
+ *  [31:2] | ???    | 0x0     | *UNDEFINED*                \r
+ * \r
+ */\r
+/*\r
+ * Field : Deep Power Down Acknowledge - deeppwrdnack\r
+ * \r
+ * This bit is set to a one after a deep power down has been executed\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB        0\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK    0x00000001\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK    0xfffffffe\r
+/* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Self-refresh Acknowledge - selfrfshack\r
+ * \r
+ * This bit is a one to indicate that the controller is in a self-refresh state.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB        1\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK    0x00000002\r
+/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK    0xfffffffd\r
+/* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_LOWPWRACK.\r
+ */\r
+struct ALT_SDR_CTL_LOWPWRACK_s\r
+{\r
+    uint32_t  deeppwrdnack :  1;  /* Deep Power Down Acknowledge */\r
+    uint32_t  selfrfshack  :  1;  /* Self-refresh Acknowledge */\r
+    uint32_t               : 30;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */\r
+typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s  ALT_SDR_CTL_LOWPWRACK_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */\r
+#define ALT_SDR_CTL_LOWPWRACK_OFST        0x58\r
+\r
+/*\r
+ * Register : Static Configuration Register - staticcfg\r
+ * \r
+ * This register controls configuration values which cannot be updated while\r
+ * transactions are flowing.\r
+ * \r
+ * You should write once to this register with the membl and eccen fields set to\r
+ * your desired configuration, and then write to the register again with membl and\r
+ * eccen and the applycfg bit set. The applycfg bit is write only.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description                \r
+ * :-------|:-------|:--------|:----------------------------\r
+ *  [1:0]  | RW     | Unknown | Memory Burst Length        \r
+ *  [2]    | RW     | Unknown | Use ECC Bits As Data       \r
+ *  [3]    | RW     | Unknown | Apply Configuration Changes\r
+ *  [31:4] | ???    | 0x0     | *UNDEFINED*                \r
+ * \r
+ */\r
+/*\r
+ * Field : Memory Burst Length - membl\r
+ * \r
+ * This field specifies the DRAM burst length. Write the following values to set\r
+ * the a burst length appropriate for the specific DRAM being used. &quot;00&quot;\r
+ * for burst length 2, &quot;01&quot; for burst length 4, &quot;10&quot; for burst\r
+ * length 8. If you set this, you must also set the membl field in the ctrlcfg\r
+ * register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK    0x00000003\r
+/* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK    0xfffffffc\r
+/* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+/*\r
+ * Field : Use ECC Bits As Data - useeccasdata\r
+ * \r
+ * This field allows the FPGA ports to directly access the extra data bits that are\r
+ * normally used to hold the ECC code. The interface width must be set to 24 or 40\r
+ * in the dramifwidth register. If you set this, you must clear the eccen field in\r
+ * the ctrlcfg register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB        2\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK    0x00000004\r
+/* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK    0xfffffffb\r
+/* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Apply Configuration Changes - applycfg\r
+ * \r
+ * Write with this bit set to apply all the settings loaded in SDR registers to the\r
+ * memory interface. This bit is write-only and always returns 0 if read.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB        3\r
+/* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK    0x00000008\r
+/* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK    0xfffffff7\r
+/* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_STATICCFG.\r
+ */\r
+struct ALT_SDR_CTL_STATICCFG_s\r
+{\r
+    uint32_t  membl        :  2;  /* Memory Burst Length */\r
+    uint32_t  useeccasdata :  1;  /* Use ECC Bits As Data */\r
+    uint32_t  applycfg     :  1;  /* Apply Configuration Changes */\r
+    uint32_t               : 28;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */\r
+typedef volatile struct ALT_SDR_CTL_STATICCFG_s  ALT_SDR_CTL_STATICCFG_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */\r
+#define ALT_SDR_CTL_STATICCFG_OFST        0x5c\r
+\r
+/*\r
+ * Register : Memory Controller Width Register - ctrlwidth\r
+ * \r
+ * This register controls the width of the physical DRAM interface.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description               \r
+ * :-------|:-------|:--------|:---------------------------\r
+ *  [1:0]  | RW     | Unknown | Controller Interface Width\r
+ *  [31:2] | ???    | 0x0     | *UNDEFINED*               \r
+ * \r
+ */\r
+/*\r
+ * Field : Controller Interface Width - ctrlwidth\r
+ * \r
+ * Specifies controller DRAM interface width, with the following encoding.\r
+ * &quot;00&quot; for 8-bit, &quot;01&quot; for 16-bit (no ECC) or 24-bit (ECC\r
+ * enabled), &quot;10&quot; for 32-bit (no ECC) or 40-bit (ECC enabled). You must\r
+ * also program the dramifwidth register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK    0x00000003\r
+/* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK    0xfffffffc\r
+/* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_CTLWIDTH.\r
+ */\r
+struct ALT_SDR_CTL_CTLWIDTH_s\r
+{\r
+    uint32_t  ctrlwidth :  2;  /* Controller Interface Width */\r
+    uint32_t            : 30;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */\r
+typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s  ALT_SDR_CTL_CTLWIDTH_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */\r
+#define ALT_SDR_CTL_CTLWIDTH_OFST        0x60\r
+\r
+/*\r
+ * Register : Port Configuration Register - portcfg\r
+ * \r
+ * This register should be set to a zero in any bit which corresponds to a port\r
+ * which does mostly sequential memory accesses.  For ports with highly random\r
+ * accesses, the bit should be set to a one.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description          \r
+ * :--------|:-------|:--------|:----------------------\r
+ *  [9:0]   | ???    | Unknown | *UNDEFINED*          \r
+ *  [19:10] | RW     | Unknown | Auto-precharge Enable\r
+ *  [31:20] | ???    | 0x0     | *UNDEFINED*          \r
+ * \r
+ */\r
+/*\r
+ * Field : Auto-precharge Enable - autopchen\r
+ * \r
+ * One bit per control port.  Set bit N to a 1 to have the controller request an\r
+ * automatic precharge following bus command completion (close the row\r
+ * automatically).  Set to a zero to request that the controller attempt to keep a\r
+ * row open.  For random dominated operations this register should be set to a 1\r
+ * for all active ports.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB        10\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB        19\r
+/* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK    0x000ffc00\r
+/* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK    0xfff003ff\r
+/* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10)\r
+/* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PORTCFG.\r
+ */\r
+struct ALT_SDR_CTL_PORTCFG_s\r
+{\r
+    uint32_t            : 10;  /* *UNDEFINED* */\r
+    uint32_t  autopchen : 10;  /* Auto-precharge Enable */\r
+    uint32_t            : 12;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */\r
+typedef volatile struct ALT_SDR_CTL_PORTCFG_s  ALT_SDR_CTL_PORTCFG_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PORTCFG_OFST        0x7c\r
+\r
+/*\r
+ * Register : FPGA Ports Reset Control Register - fpgaportrst\r
+ * \r
+ * This register implements functionality to allow the CPU to control when the MPFE\r
+ * will enable the ports to the FPGA fabric.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description       \r
+ * :--------|:-------|:--------|:-------------------\r
+ *  [13:0]  | RW     | Unknown | Port Reset Control\r
+ *  [31:14] | ???    | 0x0     | *UNDEFINED*       \r
+ * \r
+ */\r
+/*\r
+ * Field : Port Reset Control - portrstn\r
+ * \r
+ * This register should be written to with a 1 to enable the selected FPGA port to\r
+ * exit reset.  Writing a bit to a zero will stretch the port reset until the\r
+ * register is written. Read data ports are connected to bits 3:0, with read data\r
+ * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped\r
+ * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit\r
+ * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to\r
+ * command port 5 at bit 13. Expected usage would be to set all the bits at the\r
+ * same time but setting some bits to a zero and others to a one is supported.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB        13\r
+/* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH      14\r
+/* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK    0x00003fff\r
+/* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK    0xffffc000\r
+/* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0)\r
+/* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST.\r
+ */\r
+struct ALT_SDR_CTL_FPGAPORTRST_s\r
+{\r
+    uint32_t  portrstn : 14;  /* Port Reset Control */\r
+    uint32_t           : 18;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */\r
+typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s  ALT_SDR_CTL_FPGAPORTRST_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */\r
+#define ALT_SDR_CTL_FPGAPORTRST_OFST        0x80\r
+\r
+/*\r
+ * Register : Memory Protection Port Default Register - protportdefault\r
+ * \r
+ * This register controls the default protection assignment for a port.  Ports\r
+ * which have explicit rules which define regions which are illegal to access\r
+ * should set the bits to pass by default.  Ports which have explicit rules which\r
+ * define legal areas should set the bit to force all transactions to fail.\r
+ * Leaving this register to all zeros should be used for systems which do not\r
+ * desire any protection from the memory controller.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description        \r
+ * :--------|:-------|:--------|:--------------------\r
+ *  [9:0]   | RW     | Unknown | Port Default Action\r
+ *  [31:10] | ???    | 0x0     | *UNDEFINED*        \r
+ * \r
+ */\r
+/*\r
+ * Field : Port Default Action - portdefault\r
+ * \r
+ * Determines the default action for a transactions from a port.  Set a bit to a\r
+ * zero to indicate that all accesses from the port should pass by default, set a\r
+ * bit to a one if the default protection is to fail the access.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB        9\r
+/* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK    0x000003ff\r
+/* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK    0xfffffc00\r
+/* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT.\r
+ */\r
+struct ALT_SDR_CTL_PROTPORTDEFAULT_s\r
+{\r
+    uint32_t  portdefault : 10;  /* Port Default Action */\r
+    uint32_t              : 22;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */\r
+typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s  ALT_SDR_CTL_PROTPORTDEFAULT_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PROTPORTDEFAULT_OFST        0x8c\r
+\r
+/*\r
+ * Register : Memory Protection Address Register - protruleaddr\r
+ * \r
+ * This register is used to control the memory protection for port 0 transactions.\r
+ * Address ranges can either be used to allow access to memory regions or disallow\r
+ * access to memory regions.  If trustzone is being used, access can be enabled for\r
+ * protected transactions or disabled for unprotected transactions.  The default\r
+ * state of this register is to allow all access.  Address values used for\r
+ * protection are only physical addresses.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description \r
+ * :--------|:-------|:--------|:-------------\r
+ *  [11:0]  | RW     | Unknown | Low Address \r
+ *  [23:12] | RW     | Unknown | High Address\r
+ *  [31:24] | ???    | 0x0     | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Low Address - lowaddr\r
+ * \r
+ * Lower 12 bits of the address for a check.  Address is compared to be less than\r
+ * or equal to the address of a transaction.  Note that since AXI transactions\r
+ * cannot cross a 4K byte boundary, the transaction start and transaction end\r
+ * address must also fall within the same 1MByte block pointed to by this address\r
+ * pointer.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB        11\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH      12\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK    0x00000fff\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK    0xfffff000\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0)\r
+/* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff)\r
+\r
+/*\r
+ * Field : High Address - highaddr\r
+ * \r
+ * Upper 12 bits of the address for a check.  Address is compared to be greater\r
+ * than or equal to the address of a transaction.  Note that since AXI transactions\r
+ * cannot cross a 4K byte boundary, the transaction start and transaction end\r
+ * address must also fall within the same 1MByte block pointed to by this address\r
+ * pointer.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB        12\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB        23\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH      12\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK    0x00fff000\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK    0xff000fff\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12)\r
+/* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR.\r
+ */\r
+struct ALT_SDR_CTL_PROTRULEADDR_s\r
+{\r
+    uint32_t  lowaddr  : 12;  /* Low Address */\r
+    uint32_t  highaddr : 12;  /* High Address */\r
+    uint32_t           :  8;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */\r
+typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s  ALT_SDR_CTL_PROTRULEADDR_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PROTRULEADDR_OFST        0x90\r
+\r
+/*\r
+ * Register : Memory Protection ID Register - protruleid\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description\r
+ * :--------|:-------|:--------|:------------\r
+ *  [11:0]  | RW     | Unknown | Low ID     \r
+ *  [23:12] | RW     | Unknown | High ID    \r
+ *  [31:24] | ???    | 0x0     | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Low ID - lowid\r
+ * \r
+ * AxID for the protection rule.  Incoming AxID needs to be greater than or equal\r
+ * to this value.  For all AxIDs from a port, AxID high should be programmed to all\r
+ * ones.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_MSB        11\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH      12\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK    0x00000fff\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK    0xfffff000\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0)\r
+/* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff)\r
+\r
+/*\r
+ * Field : High ID - highid\r
+ * \r
+ * AxID for the protection rule.  Incoming AxID needs to be less than or equal to\r
+ * this value.  For all AxIDs from a port, AxID high should be programmed to all\r
+ * ones.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB        12\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB        23\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH      12\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK    0x00fff000\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK    0xff000fff\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12)\r
+/* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PROTRULEID.\r
+ */\r
+struct ALT_SDR_CTL_PROTRULEID_s\r
+{\r
+    uint32_t  lowid  : 12;  /* Low ID */\r
+    uint32_t  highid : 12;  /* High ID */\r
+    uint32_t         :  8;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */\r
+typedef volatile struct ALT_SDR_CTL_PROTRULEID_s  ALT_SDR_CTL_PROTRULEID_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PROTRULEID_OFST        0x94\r
+\r
+/*\r
+ * Register : Memory Protection Rule Data Register - protruledata\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description          \r
+ * :--------|:-------|:--------|:----------------------\r
+ *  [1:0]   | RW     | Unknown | Security Bit Behavior\r
+ *  [2]     | RW     | Unknown | Valid Rule           \r
+ *  [12:3]  | RW     | Unknown | Port Mask            \r
+ *  [13]    | RW     | Unknown | Rule Results         \r
+ *  [31:14] | ???    | 0x0     | *UNDEFINED*          \r
+ * \r
+ */\r
+/*\r
+ * Field : Security Bit Behavior - security\r
+ * \r
+ * A value of 2'b00 will make the rule apply to secure transactions.\r
+ * \r
+ * A value of 2'b01 will make the rule apply to non-secure transactions.\r
+ * \r
+ * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure\r
+ * transactions.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB        1\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH      2\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK    0x00000003\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK    0xfffffffc\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+/*\r
+ * Field : Valid Rule - validrule\r
+ * \r
+ * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB        2\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB        2\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK    0x00000004\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK    0xfffffffb\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Port Mask - portmask\r
+ * \r
+ * Set  bit x to a one to have this rule apply to port x, set bit x to a zero to\r
+ * have the rule not apply to a port.&#10;Note that port 0-port 5 are the FPGA\r
+ * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9\r
+ * is CPU write.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB        3\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB        12\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK    0x00001ff8\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK    0xffffe007\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3)\r
+/* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8)\r
+\r
+/*\r
+ * Field : Rule Results - ruleresult\r
+ * \r
+ * Set this bit to a one to force a protection failure, zero to allow the access\r
+ * the succeed\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB        13\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB        13\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK    0x00002000\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK    0xffffdfff\r
+/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13)\r
+/* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA.\r
+ */\r
+struct ALT_SDR_CTL_PROTRULEDATA_s\r
+{\r
+    uint32_t  security   :  2;  /* Security Bit Behavior */\r
+    uint32_t  validrule  :  1;  /* Valid Rule */\r
+    uint32_t  portmask   : 10;  /* Port Mask */\r
+    uint32_t  ruleresult :  1;  /* Rule Results */\r
+    uint32_t             : 18;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */\r
+typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s  ALT_SDR_CTL_PROTRULEDATA_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PROTRULEDATA_OFST        0x98\r
+\r
+/*\r
+ * Register : Memory Protection Rule Read-Write Register - protrulerdwr\r
+ * \r
+ * This register is used to perform read and write operations to the internal\r
+ * protection table.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description\r
+ * :-------|:-------|:--------|:------------\r
+ *  [4:0]  | RW     | Unknown | Rule Offset\r
+ *  [5]    | RW     | Unknown | Rule Write \r
+ *  [6]    | RW     | Unknown | Rule Read  \r
+ *  [31:7] | ???    | 0x0     | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Rule Offset - ruleoffset\r
+ * \r
+ * This field defines which of the 20 rules in the protection table you want to\r
+ * read or write.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB        4\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH      5\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK    0x0000001f\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK    0xffffffe0\r
+/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0)\r
+/* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f)\r
+\r
+/*\r
+ * Field : Rule Write - writerule\r
+ * \r
+ * Write to this bit to have the memory_prot_data register to the table at the\r
+ * offset specified by port_offset.  Bit automatically clears after a single cycle\r
+ * and the write operation is complete.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB        5\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB        5\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK    0x00000020\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK    0xffffffdf\r
+/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+/*\r
+ * Field : Rule Read - readrule\r
+ * \r
+ * Write to this bit to have the memory_prot_data register loaded with the value\r
+ * from the internal protection table at offset.  Table value will be loaded before\r
+ * a rdy is returned so read data from the register will be correct for any follow-\r
+ * on reads to the memory_prot_data register.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB        6\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB        6\r
+/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH      1\r
+/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK    0x00000040\r
+/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK    0xffffffbf\r
+/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR.\r
+ */\r
+struct ALT_SDR_CTL_PROTRULERDWR_s\r
+{\r
+    uint32_t  ruleoffset :  5;  /* Rule Offset */\r
+    uint32_t  writerule  :  1;  /* Rule Write */\r
+    uint32_t  readrule   :  1;  /* Rule Read */\r
+    uint32_t             : 25;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */\r
+typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s  ALT_SDR_CTL_PROTRULERDWR_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */\r
+#define ALT_SDR_CTL_PROTRULERDWR_OFST        0x9c\r
+\r
+/*\r
+ * Register : QOS Control Register - qoslowpri\r
+ * \r
+ * This register controls the mapping of AXI4 QOS received from the FPGA fabric to\r
+ * the internal priority used for traffic prioritization.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description           \r
+ * :--------|:-------|:--------|:-----------------------\r
+ *  [19:0]  | RW     | Unknown | Low Priority QoS Value\r
+ *  [31:20] | ???    | 0x0     | *UNDEFINED*           \r
+ * \r
+ */\r
+/*\r
+ * Field : Low Priority QoS Value - lowpriorityval\r
+ * \r
+ * This 20 bit field is a 2 bit field for each of the 10 ports.  The field used for\r
+ * each port in this register controls the priority used for a port\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB        19\r
+/* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH      20\r
+/* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK    0x000fffff\r
+/* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK    0xfff00000\r
+/* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI.\r
+ */\r
+struct ALT_SDR_CTL_QOSLOWPRI_s\r
+{\r
+    uint32_t  lowpriorityval : 20;  /* Low Priority QoS Value */\r
+    uint32_t                 : 12;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */\r
+typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s  ALT_SDR_CTL_QOSLOWPRI_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */\r
+#define ALT_SDR_CTL_QOSLOWPRI_OFST        0xa0\r
+\r
+/*\r
+ * Register : qoshighpri Register - qoshighpri\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description            \r
+ * :--------|:-------|:--------|:------------------------\r
+ *  [19:0]  | RW     | Unknown | High Priority QoS Value\r
+ *  [31:20] | ???    | 0x0     | *UNDEFINED*            \r
+ * \r
+ */\r
+/*\r
+ * Field : High Priority QoS Value - highpriorityval\r
+ * \r
+ * This 20 bit field is a 2 bit field for each of the 10 ports.  The field used for\r
+ * each port in this register controls the priority used for a port\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB        19\r
+/* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH      20\r
+/* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK    0x000fffff\r
+/* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK    0xfff00000\r
+/* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI.\r
+ */\r
+struct ALT_SDR_CTL_QOSHIGHPRI_s\r
+{\r
+    uint32_t  highpriorityval : 20;  /* High Priority QoS Value */\r
+    uint32_t                  : 12;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */\r
+typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s  ALT_SDR_CTL_QOSHIGHPRI_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */\r
+#define ALT_SDR_CTL_QOSHIGHPRI_OFST        0xa4\r
+\r
+/*\r
+ * Register : qospriorityen Register - qospriorityen\r
+ * \r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description        \r
+ * :--------|:-------|:--------|:--------------------\r
+ *  [9:0]   | RW     | Unknown | Per-Port QoS Enable\r
+ *  [31:10] | ???    | 0x0     | *UNDEFINED*        \r
+ * \r
+ */\r
+/*\r
+ * Field : Per-Port QoS Enable - priorityen\r
+ * \r
+ * This 10 bit field is set to a one to enable QOS usage for a port.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB        9\r
+/* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH      10\r
+/* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK    0x000003ff\r
+/* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK    0xfffffc00\r
+/* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN.\r
+ */\r
+struct ALT_SDR_CTL_QOSPRIORITYEN_s\r
+{\r
+    uint32_t  priorityen : 10;  /* Per-Port QoS Enable */\r
+    uint32_t             : 22;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */\r
+typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s  ALT_SDR_CTL_QOSPRIORITYEN_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */\r
+#define ALT_SDR_CTL_QOSPRIORITYEN_OFST        0xa8\r
+\r
+/*\r
+ * Register : Scheduler priority Register - mppriority\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description         \r
+ * :--------|:-------|:--------|:---------------------\r
+ *  [29:0]  | RW     | Unknown | Port User Priorities\r
+ *  [31:30] | ???    | 0x0     | *UNDEFINED*         \r
+ * \r
+ */\r
+/*\r
+ * Field : Port User Priorities - userpriority\r
+ * \r
+ * Set absolute user priority of the port.  Each port is represented by a 3 bit\r
+ * value, 000=lowest priority, 111=highest priority.  Port 0 is bits 2:0.  Port\r
+ * number offset corresponds to the control port assignment.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB        29\r
+/* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH      30\r
+/* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK    0x3fffffff\r
+/* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK    0xc0000000\r
+/* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_MPPRIORITY.\r
+ */\r
+struct ALT_SDR_CTL_MPPRIORITY_s\r
+{\r
+    uint32_t  userpriority : 30;  /* Port User Priorities */\r
+    uint32_t               :  2;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */\r
+typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s  ALT_SDR_CTL_MPPRIORITY_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */\r
+#define ALT_SDR_CTL_MPPRIORITY_OFST        0xac\r
+\r
+/*\r
+ * Register : Controller Command Pool Priority Remap Register - remappriority\r
+ * \r
+ * This register controls the priority for transactions in the controller command\r
+ * pool.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description   \r
+ * :-------|:-------|:--------|:---------------\r
+ *  [7:0]  | RW     | Unknown | Priority Remap\r
+ *  [31:8] | ???    | 0x0     | *UNDEFINED*   \r
+ * \r
+ */\r
+/*\r
+ * Field : Priority Remap - priorityremap\r
+ * \r
+ * Set bit N of this register to the value to a one to enable the controller\r
+ * command pool priority bit of a transaction from MPFE priority N\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB        7\r
+/* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH      8\r
+/* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK    0x000000ff\r
+/* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK    0xffffff00\r
+/* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY.\r
+ */\r
+struct ALT_SDR_CTL_REMAPPRIORITY_s\r
+{\r
+    uint32_t  priorityremap :  8;  /* Priority Remap */\r
+    uint32_t                : 24;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */\r
+typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s  ALT_SDR_CTL_REMAPPRIORITY_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */\r
+#define ALT_SDR_CTL_REMAPPRIORITY_OFST        0xe0\r
+\r
+/*\r
+ * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT\r
+ * Port Sum of Weight Register\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ */\r
+/*\r
+ * Register : Port Sum of Weight Register[1/4] - mpweight_0_4\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description              \r
+ * :-------|:-------|:--------|:--------------------------\r
+ *  [31:0] | RW     | Unknown | Port Static Weights[31:0]\r
+ * \r
+ */\r
+/*\r
+ * Field : Port Static Weights[31:0] - staticweight_31_0\r
+ * \r
+ * Set static weight of the port.  Each port is programmed with a 5 bit value.\r
+ * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH      32\r
+/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK    0xffffffff\r
+/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK    0x00000000\r
+/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4.\r
+ */\r
+struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s\r
+{\r
+    uint32_t  staticweight_31_0 : 32;  /* Port Static Weights[31:0] */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s  ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST        0x0\r
+/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))\r
+\r
+/*\r
+ * Register : Port Sum of Weight Register[2/4] - mpweight_1_4\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description               \r
+ * :--------|:-------|:--------|:---------------------------\r
+ *  [17:0]  | RW     | Unknown | Port Static Weights[49:32]\r
+ *  [31:18] | RW     | Unknown | Port Sum of Weights[13:0] \r
+ * \r
+ */\r
+/*\r
+ * Field : Port Static Weights[49:32] - staticweight_49_32\r
+ * \r
+ * Set static weight of the port.  Each port is programmed with a 5 bit value.\r
+ * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB        17\r
+/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH      18\r
+/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK    0x0003ffff\r
+/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK    0xfffc0000\r
+/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff)\r
+\r
+/*\r
+ * Field : Port Sum of Weights[13:0] - sumofweights_13_0\r
+ * \r
+ * Set the sum of static weights for particular user priority.  This register is\r
+ * used as part of the deficit round robin implementation.  It should be set to the\r
+ * sum of the weights for the ports\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB        18\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH      14\r
+/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK    0xfffc0000\r
+/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK    0x0003ffff\r
+/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18)\r
+/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4.\r
+ */\r
+struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s\r
+{\r
+    uint32_t  staticweight_49_32 : 18;  /* Port Static Weights[49:32] */\r
+    uint32_t  sumofweights_13_0  : 14;  /* Port Sum of Weights[13:0] */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s  ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST        0x4\r
+/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))\r
+\r
+/*\r
+ * Register : Port Sum of Weight Register[3/4] - mpweight_2_4\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits   | Access | Reset   | Description               \r
+ * :-------|:-------|:--------|:---------------------------\r
+ *  [31:0] | RW     | Unknown | Port Sum of Weights[45:14]\r
+ * \r
+ */\r
+/*\r
+ * Field : Port Sum of Weights[45:14] - sumofweights_45_14\r
+ * \r
+ * Set the sum of static weights for particular user priority.  This register is\r
+ * used as part of the deficit round robin implementation.  It should be set to the\r
+ * sum of the weights for the ports\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB        31\r
+/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH      32\r
+/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK    0xffffffff\r
+/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK    0x00000000\r
+/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4.\r
+ */\r
+struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s\r
+{\r
+    uint32_t  sumofweights_45_14 : 32;  /* Port Sum of Weights[45:14] */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s  ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST        0x8\r
+/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))\r
+\r
+/*\r
+ * Register : Port Sum of Weight Register[4/4] - mpweight_3_4\r
+ * \r
+ * This register is used to configure the DRAM burst operation scheduling.\r
+ * \r
+ * Register Layout\r
+ * \r
+ *  Bits    | Access | Reset   | Description               \r
+ * :--------|:-------|:--------|:---------------------------\r
+ *  [17:0]  | RW     | Unknown | Port Sum of Weights[63:46]\r
+ *  [31:18] | ???    | 0x0     | *UNDEFINED*               \r
+ * \r
+ */\r
+/*\r
+ * Field : Port Sum of Weights[63:46] - sumofweights_63_46\r
+ * \r
+ * Set the sum of static weights for particular user priority.  This register is\r
+ * used as part of the deficit round robin implementation.  It should be set to the\r
+ * sum of the weights for the ports\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB        0\r
+/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB        17\r
+/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH      18\r
+/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK    0x0003ffff\r
+/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK    0xfffc0000\r
+/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET      0x0\r
+/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0)\r
+/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4.\r
+ */\r
+struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s\r
+{\r
+    uint32_t  sumofweights_63_46 : 18;  /* Port Sum of Weights[63:46] */\r
+    uint32_t                     : 14;  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s  ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST        0xc\r
+/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */\r
+#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_SDR_CTL_MPWT.\r
+ */\r
+struct ALT_SDR_CTL_MPWT_s\r
+{\r
+    volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t  mpweight_0_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */\r
+    volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t  mpweight_1_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */\r
+    volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t  mpweight_2_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */\r
+    volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t  mpweight_3_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_SDR_CTL_MPWT. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_s  ALT_SDR_CTL_MPWT_t;\r
+/* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */\r
+struct ALT_SDR_CTL_MPWT_raw_s\r
+{\r
+    volatile uint32_t  mpweight_0_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */\r
+    volatile uint32_t  mpweight_1_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */\r
+    volatile uint32_t  mpweight_2_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */\r
+    volatile uint32_t  mpweight_3_4;  /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */\r
+typedef volatile struct ALT_SDR_CTL_MPWT_raw_s  ALT_SDR_CTL_MPWT_raw_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_SDR_CTL.\r
+ */\r
+struct ALT_SDR_CTL_s\r
+{\r
+    volatile ALT_SDR_CTL_CTLCFG_t           ctrlcfg;                /* ALT_SDR_CTL_CTLCFG */\r
+    volatile ALT_SDR_CTL_DRAMTIMING1_t      dramtiming1;            /* ALT_SDR_CTL_DRAMTIMING1 */\r
+    volatile ALT_SDR_CTL_DRAMTIMING2_t      dramtiming2;            /* ALT_SDR_CTL_DRAMTIMING2 */\r
+    volatile ALT_SDR_CTL_DRAMTIMING3_t      dramtiming3;            /* ALT_SDR_CTL_DRAMTIMING3 */\r
+    volatile ALT_SDR_CTL_DRAMTIMING4_t      dramtiming4;            /* ALT_SDR_CTL_DRAMTIMING4 */\r
+    volatile ALT_SDR_CTL_LOWPWRTIMING_t     lowpwrtiming;           /* ALT_SDR_CTL_LOWPWRTIMING */\r
+    volatile ALT_SDR_CTL_DRAMODT_t          dramodt;                /* ALT_SDR_CTL_DRAMODT */\r
+    volatile uint32_t                       _pad_0x1c_0x2b[4];      /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_DRAMADDRW_t        dramaddrw;              /* ALT_SDR_CTL_DRAMADDRW */\r
+    volatile ALT_SDR_CTL_DRAMIFWIDTH_t      dramifwidth;            /* ALT_SDR_CTL_DRAMIFWIDTH */\r
+    volatile ALT_SDR_CTL_DRAMDEVWIDTH_t     dramdevwidth;           /* ALT_SDR_CTL_DRAMDEVWIDTH */\r
+    volatile ALT_SDR_CTL_DRAMSTS_t          dramsts;                /* ALT_SDR_CTL_DRAMSTS */\r
+    volatile ALT_SDR_CTL_DRAMINTR_t         dramintr;               /* ALT_SDR_CTL_DRAMINTR */\r
+    volatile ALT_SDR_CTL_SBECOUNT_t         sbecount;               /* ALT_SDR_CTL_SBECOUNT */\r
+    volatile ALT_SDR_CTL_DBECOUNT_t         dbecount;               /* ALT_SDR_CTL_DBECOUNT */\r
+    volatile ALT_SDR_CTL_ERRADDR_t          erraddr;                /* ALT_SDR_CTL_ERRADDR */\r
+    volatile ALT_SDR_CTL_DROPCOUNT_t        dropcount;              /* ALT_SDR_CTL_DROPCOUNT */\r
+    volatile ALT_SDR_CTL_DROPADDR_t         dropaddr;               /* ALT_SDR_CTL_DROPADDR */\r
+    volatile ALT_SDR_CTL_LOWPWREQ_t         lowpwreq;               /* ALT_SDR_CTL_LOWPWREQ */\r
+    volatile ALT_SDR_CTL_LOWPWRACK_t        lowpwrack;              /* ALT_SDR_CTL_LOWPWRACK */\r
+    volatile ALT_SDR_CTL_STATICCFG_t        staticcfg;              /* ALT_SDR_CTL_STATICCFG */\r
+    volatile ALT_SDR_CTL_CTLWIDTH_t         ctrlwidth;              /* ALT_SDR_CTL_CTLWIDTH */\r
+    volatile uint32_t                       _pad_0x64_0x7b[6];      /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_PORTCFG_t          portcfg;                /* ALT_SDR_CTL_PORTCFG */\r
+    volatile ALT_SDR_CTL_FPGAPORTRST_t      fpgaportrst;            /* ALT_SDR_CTL_FPGAPORTRST */\r
+    volatile uint32_t                       _pad_0x84_0x8b[2];      /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_PROTPORTDEFAULT_t  protportdefault;        /* ALT_SDR_CTL_PROTPORTDEFAULT */\r
+    volatile ALT_SDR_CTL_PROTRULEADDR_t     protruleaddr;           /* ALT_SDR_CTL_PROTRULEADDR */\r
+    volatile ALT_SDR_CTL_PROTRULEID_t       protruleid;             /* ALT_SDR_CTL_PROTRULEID */\r
+    volatile ALT_SDR_CTL_PROTRULEDATA_t     protruledata;           /* ALT_SDR_CTL_PROTRULEDATA */\r
+    volatile ALT_SDR_CTL_PROTRULERDWR_t     protrulerdwr;           /* ALT_SDR_CTL_PROTRULERDWR */\r
+    volatile ALT_SDR_CTL_QOSLOWPRI_t        qoslowpri;              /* ALT_SDR_CTL_QOSLOWPRI */\r
+    volatile ALT_SDR_CTL_QOSHIGHPRI_t       qoshighpri;             /* ALT_SDR_CTL_QOSHIGHPRI */\r
+    volatile ALT_SDR_CTL_QOSPRIORITYEN_t    qospriorityen;          /* ALT_SDR_CTL_QOSPRIORITYEN */\r
+    volatile ALT_SDR_CTL_MPPRIORITY_t       mppriority;             /* ALT_SDR_CTL_MPPRIORITY */\r
+    volatile ALT_SDR_CTL_MPWT_t             ctrlgrp_mpweight;       /* ALT_SDR_CTL_MPWT */\r
+    volatile uint32_t                       _pad_0xc0_0xdf[8];      /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_REMAPPRIORITY_t    remappriority;          /* ALT_SDR_CTL_REMAPPRIORITY */\r
+    volatile uint32_t                       _pad_0xe4_0x1000[967];  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_SDR_CTL. */\r
+typedef volatile struct ALT_SDR_CTL_s  ALT_SDR_CTL_t;\r
+/* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */\r
+struct ALT_SDR_CTL_raw_s\r
+{\r
+    volatile uint32_t                ctrlcfg;                /* ALT_SDR_CTL_CTLCFG */\r
+    volatile uint32_t                dramtiming1;            /* ALT_SDR_CTL_DRAMTIMING1 */\r
+    volatile uint32_t                dramtiming2;            /* ALT_SDR_CTL_DRAMTIMING2 */\r
+    volatile uint32_t                dramtiming3;            /* ALT_SDR_CTL_DRAMTIMING3 */\r
+    volatile uint32_t                dramtiming4;            /* ALT_SDR_CTL_DRAMTIMING4 */\r
+    volatile uint32_t                lowpwrtiming;           /* ALT_SDR_CTL_LOWPWRTIMING */\r
+    volatile uint32_t                dramodt;                /* ALT_SDR_CTL_DRAMODT */\r
+    volatile uint32_t                _pad_0x1c_0x2b[4];      /* *UNDEFINED* */\r
+    volatile uint32_t                dramaddrw;              /* ALT_SDR_CTL_DRAMADDRW */\r
+    volatile uint32_t                dramifwidth;            /* ALT_SDR_CTL_DRAMIFWIDTH */\r
+    volatile uint32_t                dramdevwidth;           /* ALT_SDR_CTL_DRAMDEVWIDTH */\r
+    volatile uint32_t                dramsts;                /* ALT_SDR_CTL_DRAMSTS */\r
+    volatile uint32_t                dramintr;               /* ALT_SDR_CTL_DRAMINTR */\r
+    volatile uint32_t                sbecount;               /* ALT_SDR_CTL_SBECOUNT */\r
+    volatile uint32_t                dbecount;               /* ALT_SDR_CTL_DBECOUNT */\r
+    volatile uint32_t                erraddr;                /* ALT_SDR_CTL_ERRADDR */\r
+    volatile uint32_t                dropcount;              /* ALT_SDR_CTL_DROPCOUNT */\r
+    volatile uint32_t                dropaddr;               /* ALT_SDR_CTL_DROPADDR */\r
+    volatile uint32_t                lowpwreq;               /* ALT_SDR_CTL_LOWPWREQ */\r
+    volatile uint32_t                lowpwrack;              /* ALT_SDR_CTL_LOWPWRACK */\r
+    volatile uint32_t                staticcfg;              /* ALT_SDR_CTL_STATICCFG */\r
+    volatile uint32_t                ctrlwidth;              /* ALT_SDR_CTL_CTLWIDTH */\r
+    volatile uint32_t                _pad_0x64_0x7b[6];      /* *UNDEFINED* */\r
+    volatile uint32_t                portcfg;                /* ALT_SDR_CTL_PORTCFG */\r
+    volatile uint32_t                fpgaportrst;            /* ALT_SDR_CTL_FPGAPORTRST */\r
+    volatile uint32_t                _pad_0x84_0x8b[2];      /* *UNDEFINED* */\r
+    volatile uint32_t                protportdefault;        /* ALT_SDR_CTL_PROTPORTDEFAULT */\r
+    volatile uint32_t                protruleaddr;           /* ALT_SDR_CTL_PROTRULEADDR */\r
+    volatile uint32_t                protruleid;             /* ALT_SDR_CTL_PROTRULEID */\r
+    volatile uint32_t                protruledata;           /* ALT_SDR_CTL_PROTRULEDATA */\r
+    volatile uint32_t                protrulerdwr;           /* ALT_SDR_CTL_PROTRULERDWR */\r
+    volatile uint32_t                qoslowpri;              /* ALT_SDR_CTL_QOSLOWPRI */\r
+    volatile uint32_t                qoshighpri;             /* ALT_SDR_CTL_QOSHIGHPRI */\r
+    volatile uint32_t                qospriorityen;          /* ALT_SDR_CTL_QOSPRIORITYEN */\r
+    volatile uint32_t                mppriority;             /* ALT_SDR_CTL_MPPRIORITY */\r
+    volatile ALT_SDR_CTL_MPWT_raw_t  ctrlgrp_mpweight;       /* ALT_SDR_CTL_MPWT */\r
+    volatile uint32_t                _pad_0xc0_0xdf[8];      /* *UNDEFINED* */\r
+    volatile uint32_t                remappriority;          /* ALT_SDR_CTL_REMAPPRIORITY */\r
+    volatile uint32_t                _pad_0xe4_0x1000[967];  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */\r
+typedef volatile struct ALT_SDR_CTL_raw_s  ALT_SDR_CTL_raw_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_SDR.\r
+ */\r
+struct ALT_SDR_s\r
+{\r
+    volatile uint32_t       _pad_0x0_0x4fff[5120];       /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_t  ctrlgrp;                     /* ALT_SDR_CTL */\r
+    volatile uint32_t       _pad_0x6000_0x20000[26624];  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_SDR. */\r
+typedef volatile struct ALT_SDR_s  ALT_SDR_t;\r
+/* The struct declaration for the raw register contents of register group ALT_SDR. */\r
+struct ALT_SDR_raw_s\r
+{\r
+    volatile uint32_t           _pad_0x0_0x4fff[5120];       /* *UNDEFINED* */\r
+    volatile ALT_SDR_CTL_raw_t  ctrlgrp;                     /* ALT_SDR_CTL */\r
+    volatile uint32_t           _pad_0x6000_0x20000[26624];  /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_SDR. */\r
+typedef volatile struct ALT_SDR_raw_s  ALT_SDR_raw_t;\r
+#endif  /* __ASSEMBLY__ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif  /* __cplusplus */\r
+#endif  /* __ALTERA_ALT_SDR_H__ */\r
+\r