--- /dev/null
+/*******************************************************************************\r
+* *\r
+* Copyright 2013 Altera Corporation. All Rights Reserved. *\r
+* *\r
+* Redistribution and use in source and binary forms, with or without *\r
+* modification, are permitted provided that the following conditions are met: *\r
+* *\r
+* 1. Redistributions of source code must retain the above copyright notice, *\r
+* this list of conditions and the following disclaimer. *\r
+* *\r
+* 2. Redistributions in binary form must reproduce the above copyright notice, *\r
+* this list of conditions and the following disclaimer in the documentation *\r
+* and/or other materials provided with the distribution. *\r
+* *\r
+* 3. The name of the author may not be used to endorse or promote products *\r
+* derived from this software without specific prior written permission. *\r
+* *\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *\r
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *\r
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *\r
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *\r
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *\r
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *\r
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *\r
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *\r
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *\r
+* *\r
+*******************************************************************************/\r
+\r
+/* Altera - ALT_UART */\r
+\r
+#ifndef __ALTERA_ALT_UART_H__\r
+#define __ALTERA_ALT_UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif /* __cplusplus */\r
+\r
+/*\r
+ * Component : UART Module - ALT_UART\r
+ * UART Module\r
+ * \r
+ * Registers in the UART module\r
+ * \r
+ */\r
+/*\r
+ * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll\r
+ * \r
+ * This is a multi-function register. This register holds receives and transmit\r
+ * data and controls the least-signficant 8 bits of the baud rate divisor.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description\r
+ * :-------|:-------|:------|:------------\r
+ * [7:0] | RW | 0x0 | Value \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED*\r
+ * \r
+ */\r
+/*\r
+ * Field : Value - value\r
+ * \r
+ * Receive Buffer Register:\r
+ * \r
+ * This register contains the data byte received on the serial input port\r
+ * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0]\r
+ * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of\r
+ * Register FCR is set to 0) the data in the RBR must be read before the next data\r
+ * arrives, otherwise it will be overwritten, resulting in an overrun error. If\r
+ * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses\r
+ * the head of the receive FIFO. If the receive FIFO is full, and this register is\r
+ * not read before the next data character arrives, then the data already in the\r
+ * FIFO will be preserved but any incoming data will be lost. An overrun error will\r
+ * also occur.\r
+ * \r
+ * Transmit Holding Register:\r
+ * \r
+ * This register contains data to be transmitted on the serial output port. Data\r
+ * should only be written to the THR when the THR Empty bit [5] of the LSR Register\r
+ * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and\r
+ * THRE is set to 1, writing a single character to the THR clears the THRE. Any\r
+ * additional writes to the THR before the THRE is set again causes the THR data to\r
+ * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and\r
+ * THRE is set up to 128 characters of data may be written to the THR before the\r
+ * FIFO is full. Any attempt to write data when the FIFO is full results in the\r
+ * write data being lost.\r
+ * \r
+ * Divisor Latch Low:\r
+ * \r
+ * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch\r
+ * register that contains the baud rate divisor for the UART. This register may\r
+ * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The\r
+ * output baud rate is equal to the serial clock l4_sp_clk frequency divided by\r
+ * sixteen times the value of the baud rate divisor, as follows:\r
+ * \r
+ * baud rate = (serial clock freq) / (16 * divisor)\r
+ * \r
+ * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud\r
+ * clock is disabled and no serial communications will occur. Also, once the DLL is\r
+ * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before\r
+ * transmitting or receiving data.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7\r
+/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8\r
+/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0\r
+/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */\r
+#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_RBR_THR_DLL.\r
+ */\r
+struct ALT_UART_RBR_THR_DLL_s\r
+{\r
+ uint32_t value : 8; /* Value */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */\r
+typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */\r
+#define ALT_UART_RBR_THR_DLL_OFST 0x0\r
+/* The address of the ALT_UART_RBR_THR_DLL register. */\r
+#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST))\r
+\r
+/*\r
+ * Register : Interrupt Enable and Divisor Latch High - ier_dlh\r
+ * \r
+ * This is a multi-function register. This register enables/disables receive and\r
+ * transmit interrupts and also controls the most-significant 8-bits of the baud\r
+ * rate divisor.\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * This register is accessed when the DLAB bit [7] of the LCR Register is set to\r
+ * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output\r
+ * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen\r
+ * times the value of the baud rate divisor, as follows:\r
+ * \r
+ * baud rate = (serial clock freq) / (16 * divisor):\r
+ * \r
+ * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud\r
+ * clock is disabled and no serial communications will occur. Also, once the DLL is\r
+ * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before\r
+ * transmitting or receiving data.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * This register may only be accessed when the DLAB bit [7] of the LCR Register is\r
+ * set to 0.Allows control of the Interrupt Enables for transmit and receive\r
+ * functions.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------------------------------\r
+ * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable \r
+ * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control \r
+ * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status \r
+ * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt \r
+ * [4] | RW | 0x0 | DLH[4] \r
+ * [5] | RW | 0x0 | DLH[5] \r
+ * [6] | RW | 0x0 | DLH[6] \r
+ * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * Bit 0 of DLH value.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * Used to enable/disable the generation of the Receive Data Available Interrupt\r
+ * and the Character Timeout Interrupt(if FIFO's enabled). These are the second\r
+ * highest priority interrupts.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------------|:------|:------------------\r
+ * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable\r
+ * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0\r
+ * \r
+ * Interrupt Disable\r
+ */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0\r
+ * \r
+ * Interrupt Enable\r
+ */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0\r
+/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * Bit 1 of DLH value.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable\r
+ * the generation of Transmitter Holding Register Empty Interrupt. This is the\r
+ * third highest priority interrupt.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description\r
+ * :-----------------------------------|:------|:------------\r
+ * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable \r
+ * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL\r
+ * \r
+ * Tx disable\r
+ */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL\r
+ * \r
+ * Tx enable\r
+ */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1\r
+/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * Bit 2 of DLH value.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * This is used to enable/disable the generation of Receiver Line Status Interrupt.\r
+ * This is the highest priority interrupt.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------------|:------|:----------------------------\r
+ * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat\r
+ * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2\r
+ * \r
+ * Disable interrupt line stat\r
+ */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2\r
+ * \r
+ * Enable interrupt line stat\r
+ */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2\r
+/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * Bit 3 of DLH value.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * This is used to enable/disable the generation of Modem Status Interrupts. This\r
+ * is the fourth highest priority interrupt.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------------|:------|:-------------------------------\r
+ * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt\r
+ * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3\r
+ * \r
+ * disable modem status interrupt\r
+ */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3\r
+ * \r
+ * enable modem status interrupt\r
+ */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3\r
+/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : DLH[4] - dlh4\r
+ * \r
+ * Bit 4 of DLH value.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */\r
+#define ALT_UART_IER_DLH_DLH4_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */\r
+#define ALT_UART_IER_DLH_DLH4_MSB 4\r
+/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */\r
+#define ALT_UART_IER_DLH_DLH4_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */\r
+#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */\r
+#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */\r
+#define ALT_UART_IER_DLH_DLH4_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */\r
+#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : DLH[5] - dlh5\r
+ * \r
+ * Bit 5 of DLH value.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */\r
+#define ALT_UART_IER_DLH_DLH5_LSB 5\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */\r
+#define ALT_UART_IER_DLH_DLH5_MSB 5\r
+/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */\r
+#define ALT_UART_IER_DLH_DLH5_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */\r
+#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020\r
+/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */\r
+#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf\r
+/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */\r
+#define ALT_UART_IER_DLH_DLH5_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */\r
+#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+/*\r
+ * Field : DLH[6] - dlh6\r
+ * \r
+ * Bit 6 of DLH value.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */\r
+#define ALT_UART_IER_DLH_DLH6_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */\r
+#define ALT_UART_IER_DLH_DLH6_MSB 6\r
+/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */\r
+#define ALT_UART_IER_DLH_DLH6_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */\r
+#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040\r
+/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */\r
+#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf\r
+/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */\r
+#define ALT_UART_IER_DLH_DLH6_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */\r
+#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+/*\r
+ * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7\r
+ * \r
+ * Divisor Latch High Register:\r
+ * \r
+ * Bit 7 of DLH value.\r
+ * \r
+ * Interrupt Enable Register:\r
+ * \r
+ * This is used to enable/disable the generation of THRE Interrupt.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------------|:------|:------------------------------------\r
+ * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt\r
+ * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7\r
+ * \r
+ * disable tx-hold-reg-empty interrupt\r
+ */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7\r
+ * \r
+ * enable tx-hold-reg-empty interrupt\r
+ */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7\r
+/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1\r
+/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080\r
+/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f\r
+/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0\r
+/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7)\r
+/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */\r
+#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_IER_DLH.\r
+ */\r
+struct ALT_UART_IER_DLH_s\r
+{\r
+ uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */\r
+ uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */\r
+ uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */\r
+ uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */\r
+ uint32_t dlh4 : 1; /* DLH[4] */\r
+ uint32_t dlh5 : 1; /* DLH[5] */\r
+ uint32_t dlh6 : 1; /* DLH[6] */\r
+ uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_IER_DLH. */\r
+typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */\r
+#define ALT_UART_IER_DLH_OFST 0x4\r
+/* The address of the ALT_UART_IER_DLH register. */\r
+#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))\r
+\r
+/*\r
+ * Register : Interrupt Identity Register (when read) - iir\r
+ * \r
+ * Returns interrupt identification and FIFO enable/disable when read.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------\r
+ * [3:0] | R | 0x1 | Interrupt ID\r
+ * [5:4] | ??? | 0x0 | *UNDEFINED* \r
+ * [7:6] | R | 0x0 | FIFO Enabled\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Interrupt ID - id\r
+ * \r
+ * This indicates the highest priority pending interrupt.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------------|:------|:-----------------------\r
+ * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status \r
+ * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending \r
+ * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty \r
+ * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available\r
+ * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status \r
+ * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * Modem status\r
+ */\r
+#define ALT_UART_IIR_ID_E_MODMSTAT 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * No Interrupt pending\r
+ */\r
+#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * THR empty\r
+ */\r
+#define ALT_UART_IIR_ID_E_THREMPTY 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * Receive data available\r
+ */\r
+#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * Receive line status\r
+ */\r
+#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_ID\r
+ * \r
+ * Character timeout\r
+ */\r
+#define ALT_UART_IIR_ID_E_CHARTMO 0xc\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */\r
+#define ALT_UART_IIR_ID_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */\r
+#define ALT_UART_IIR_ID_MSB 3\r
+/* The width in bits of the ALT_UART_IIR_ID register field. */\r
+#define ALT_UART_IIR_ID_WIDTH 4\r
+/* The mask used to set the ALT_UART_IIR_ID register field value. */\r
+#define ALT_UART_IIR_ID_SET_MSK 0x0000000f\r
+/* The mask used to clear the ALT_UART_IIR_ID register field value. */\r
+#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0\r
+/* The reset value of the ALT_UART_IIR_ID register field. */\r
+#define ALT_UART_IIR_ID_RESET 0x1\r
+/* Extracts the ALT_UART_IIR_ID field value from a register. */\r
+#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0)\r
+/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */\r
+#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f)\r
+\r
+/*\r
+ * Field : FIFO Enabled - fifoen\r
+ * \r
+ * This is used to indicate whether the FIFO's are enabled or disabled.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:--------------\r
+ * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled\r
+ * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_FIFOEN\r
+ * \r
+ * FIFO disabled\r
+ */\r
+#define ALT_UART_IIR_FIFOEN_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_IIR_FIFOEN\r
+ * \r
+ * FIFO enabled\r
+ */\r
+#define ALT_UART_IIR_FIFOEN_E_END 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */\r
+#define ALT_UART_IIR_FIFOEN_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */\r
+#define ALT_UART_IIR_FIFOEN_MSB 7\r
+/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */\r
+#define ALT_UART_IIR_FIFOEN_WIDTH 2\r
+/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */\r
+#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0\r
+/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */\r
+#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f\r
+/* The reset value of the ALT_UART_IIR_FIFOEN register field. */\r
+#define ALT_UART_IIR_FIFOEN_RESET 0x0\r
+/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */\r
+#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6)\r
+/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */\r
+#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_IIR.\r
+ */\r
+struct ALT_UART_IIR_s\r
+{\r
+ const uint32_t id : 4; /* Interrupt ID */\r
+ uint32_t : 2; /* *UNDEFINED* */\r
+ const uint32_t fifoen : 2; /* FIFO Enabled */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_IIR. */\r
+typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */\r
+#define ALT_UART_IIR_OFST 0x8\r
+/* The address of the ALT_UART_IIR register. */\r
+#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST))\r
+\r
+/*\r
+ * Register : FIFO Control (when written) - fcr\r
+ * \r
+ * Controls FIFO Operations when written.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:--------|:-----------------------\r
+ * [0] | W | Unknown | FIFO Enable \r
+ * [1] | W | Unknown | Rx FIFO Reset \r
+ * [2] | W | Unknown | Tx FIFO Reset \r
+ * [3] | W | Unknown | DMA Mode \r
+ * [5:4] | W | Unknown | Tx Empty Trigger Level\r
+ * [7:6] | W | Unknown | Rx Trigger Level \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : FIFO Enable - fifoe\r
+ * \r
+ * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value\r
+ * of this bit is changed both the Tx and Rx controller portion of FIFO's will be\r
+ * reset.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:---------------\r
+ * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled\r
+ * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_FIFOE\r
+ * \r
+ * FIFOs disabled\r
+ */\r
+#define ALT_UART_FCR_FIFOE_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_FIFOE\r
+ * \r
+ * FIFOs enabled\r
+ */\r
+#define ALT_UART_FCR_FIFOE_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */\r
+#define ALT_UART_FCR_FIFOE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */\r
+#define ALT_UART_FCR_FIFOE_MSB 0\r
+/* The width in bits of the ALT_UART_FCR_FIFOE register field. */\r
+#define ALT_UART_FCR_FIFOE_WIDTH 1\r
+/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */\r
+#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */\r
+#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */\r
+#define ALT_UART_FCR_FIFOE_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */\r
+#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Rx FIFO Reset - rfifor\r
+ * \r
+ * Resets the control portion of the receive FIFO and treats the FIFO as empty.\r
+ * This will also de-assert the DMA Rxrequest and single signals. Note that this\r
+ * bit is self-clearing' and it is not necessary to clear this bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:----------------------------\r
+ * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control\r
+ * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RFIFOR\r
+ * \r
+ * No Reset of Rx FIFO Control\r
+ */\r
+#define ALT_UART_FCR_RFIFOR_E_NORST 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RFIFOR\r
+ * \r
+ * Resets of Rx FIFO Control\r
+ */\r
+#define ALT_UART_FCR_RFIFOR_E_RST 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */\r
+#define ALT_UART_FCR_RFIFOR_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */\r
+#define ALT_UART_FCR_RFIFOR_MSB 1\r
+/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */\r
+#define ALT_UART_FCR_RFIFOR_WIDTH 1\r
+/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */\r
+#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */\r
+#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */\r
+#define ALT_UART_FCR_RFIFOR_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */\r
+#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Tx FIFO Reset - xfifor\r
+ * \r
+ * Resets the control portion of the transmit FIFO and treats the FIFO as empty.\r
+ * This will also de-assert the DMA Tx request and single signals when additional\r
+ * DMA handshaking is used.\r
+ * \r
+ * Note that this bit is 'self-clearing' and it is not necessary to clear this bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:----------------------------\r
+ * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control\r
+ * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_XFIFOR\r
+ * \r
+ * No Reset of Tx FIFO Control\r
+ */\r
+#define ALT_UART_FCR_XFIFOR_E_NORST 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_XFIFOR\r
+ * \r
+ * Resets Tx FIFO Control\r
+ */\r
+#define ALT_UART_FCR_XFIFOR_E_RST 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */\r
+#define ALT_UART_FCR_XFIFOR_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */\r
+#define ALT_UART_FCR_XFIFOR_MSB 2\r
+/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */\r
+#define ALT_UART_FCR_XFIFOR_WIDTH 1\r
+/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */\r
+#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */\r
+#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */\r
+#define ALT_UART_FCR_XFIFOR_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */\r
+#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : DMA Mode - dmam\r
+ * \r
+ * This determines the DMA signalling mode used for the uart_dma_tx_req_n and\r
+ * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not\r
+ * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0,\r
+ * the uart_dma_tx_req_n signal goes active low under the following conditions:\r
+ * \r
+ * * When the Transmitter Holding Register is empty in non-FIFO mode.\r
+ * \r
+ * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE\r
+ * interrupt mode disabled.\r
+ * \r
+ * * When the transmitter FIFO is at or below the programmed threshold with\r
+ * Programmable THRE interrupt mode enabled.\r
+ * \r
+ * It goes inactive under the following conditions\r
+ * \r
+ * * When a single character has been written into the Transmitter Holding\r
+ * Register or transmitter FIFO with Programmable THRE interrupt mode disabled.\r
+ * \r
+ * * When the transmitter FIFO is above the threshold with Programmable THRE\r
+ * interrupt mode enabled.\r
+ * \r
+ * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made\r
+ * continuously until the receiver FIFO has been emptied or the transmit FIFO has\r
+ * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the\r
+ * following conditions:\r
+ * \r
+ * * When the transmitter FIFO is empty with Programmable THRE interrupt mode\r
+ * disabled.\r
+ * \r
+ * * When the transmitter FIFO is at or below the programmed threshold with\r
+ * Programmable THRE interrupt mode enabled.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:---------------------------\r
+ * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode \r
+ * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_DMAM\r
+ * \r
+ * Single DMA Transfer Mode\r
+ */\r
+#define ALT_UART_FCR_DMAM_E_SINGLE 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_DMAM\r
+ * \r
+ * Multiple DMA Transfer Mode\r
+ */\r
+#define ALT_UART_FCR_DMAM_E_MULT 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */\r
+#define ALT_UART_FCR_DMAM_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */\r
+#define ALT_UART_FCR_DMAM_MSB 3\r
+/* The width in bits of the ALT_UART_FCR_DMAM register field. */\r
+#define ALT_UART_FCR_DMAM_WIDTH 1\r
+/* The mask used to set the ALT_UART_FCR_DMAM register field value. */\r
+#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */\r
+#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */\r
+#define ALT_UART_FCR_DMAM_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_DMAM field value from a register. */\r
+#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Tx Empty Trigger Level - tet\r
+ * \r
+ * This is used to select the empty threshold level at which the THRE Interrupts\r
+ * will be generated when the mode is active. It also determines when the uart DMA\r
+ * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes\r
+ * of operation.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------------|:------|:-----------------------\r
+ * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty \r
+ * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO\r
+ * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full \r
+ * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_TET\r
+ * \r
+ * FIFO empty\r
+ */\r
+#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_TET\r
+ * \r
+ * Two characters in FIFO\r
+ */\r
+#define ALT_UART_FCR_TET_E_TWOCHARS 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_TET\r
+ * \r
+ * FIFO 1/4 full\r
+ */\r
+#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_TET\r
+ * \r
+ * FIFO 1/2 full\r
+ */\r
+#define ALT_UART_FCR_TET_E_HALFFULL 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */\r
+#define ALT_UART_FCR_TET_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */\r
+#define ALT_UART_FCR_TET_MSB 5\r
+/* The width in bits of the ALT_UART_FCR_TET register field. */\r
+#define ALT_UART_FCR_TET_WIDTH 2\r
+/* The mask used to set the ALT_UART_FCR_TET register field value. */\r
+#define ALT_UART_FCR_TET_SET_MSK 0x00000030\r
+/* The mask used to clear the ALT_UART_FCR_TET register field value. */\r
+#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf\r
+/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */\r
+#define ALT_UART_FCR_TET_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_TET field value from a register. */\r
+#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4)\r
+/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030)\r
+\r
+/*\r
+ * Field : Rx Trigger Level - rt\r
+ * \r
+ * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT):\r
+ * This is used to select the trigger level in the receiver FIFO at which the\r
+ * Received Data Available Interrupt will be generated. In auto flow control mode\r
+ * it is used to determine when the uart_rts_n signal will be de-asserted. It also\r
+ * determines when the uart_dma_rx_req_n signal will be asserted when in certain\r
+ * modes of operation.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------------|:------|:----------------------\r
+ * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo\r
+ * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full \r
+ * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full \r
+ * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RT\r
+ * \r
+ * one character in fifo\r
+ */\r
+#define ALT_UART_FCR_RT_E_ONECHAR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RT\r
+ * \r
+ * FIFO 1/4 full\r
+ */\r
+#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RT\r
+ * \r
+ * FIFO 1/2 full\r
+ */\r
+#define ALT_UART_FCR_RT_E_HALFFULL 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_FCR_RT\r
+ * \r
+ * FIFO 2 less than full\r
+ */\r
+#define ALT_UART_FCR_RT_E_FULLLESS2 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */\r
+#define ALT_UART_FCR_RT_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */\r
+#define ALT_UART_FCR_RT_MSB 7\r
+/* The width in bits of the ALT_UART_FCR_RT register field. */\r
+#define ALT_UART_FCR_RT_WIDTH 2\r
+/* The mask used to set the ALT_UART_FCR_RT register field value. */\r
+#define ALT_UART_FCR_RT_SET_MSK 0x000000c0\r
+/* The mask used to clear the ALT_UART_FCR_RT register field value. */\r
+#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f\r
+/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */\r
+#define ALT_UART_FCR_RT_RESET 0x0\r
+/* Extracts the ALT_UART_FCR_RT field value from a register. */\r
+#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6)\r
+/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */\r
+#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_FCR.\r
+ */\r
+struct ALT_UART_FCR_s\r
+{\r
+ uint32_t fifoe : 1; /* FIFO Enable */\r
+ uint32_t rfifor : 1; /* Rx FIFO Reset */\r
+ uint32_t xfifor : 1; /* Tx FIFO Reset */\r
+ uint32_t dmam : 1; /* DMA Mode */\r
+ uint32_t tet : 2; /* Tx Empty Trigger Level */\r
+ uint32_t rt : 2; /* Rx Trigger Level */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_FCR. */\r
+typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */\r
+#define ALT_UART_FCR_OFST 0x8\r
+/* The address of the ALT_UART_FCR register. */\r
+#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))\r
+\r
+/*\r
+ * Register : Line Control Register (When Written) - lcr\r
+ * \r
+ * Formats serial data.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------------------\r
+ * [1:0] | RW | 0x0 | Data Length Select \r
+ * [2] | RW | 0x0 | Stop Bits \r
+ * [3] | RW | 0x0 | Parity Enable \r
+ * [4] | RW | 0x0 | Even Parity Select \r
+ * [5] | ??? | 0x0 | *UNDEFINED* \r
+ * [6] | RW | 0x0 | Break Control Bit \r
+ * [7] | RW | 0x0 | Divisor Latch Access Bit\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Data Length Select - dls\r
+ * \r
+ * Data Length Select.Selects the number of data bits per character that the\r
+ * peripheral will transmit and receive.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description\r
+ * :------------------------|:------|:------------\r
+ * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits \r
+ * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits \r
+ * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits \r
+ * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_DLS\r
+ * \r
+ * 5 bits\r
+ */\r
+#define ALT_UART_LCR_DLS_E_LEN5 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_DLS\r
+ * \r
+ * 6 bits\r
+ */\r
+#define ALT_UART_LCR_DLS_E_LEN6 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_DLS\r
+ * \r
+ * 7 bits\r
+ */\r
+#define ALT_UART_LCR_DLS_E_LEN7 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_DLS\r
+ * \r
+ * 8 bits\r
+ */\r
+#define ALT_UART_LCR_DLS_E_LEN8 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */\r
+#define ALT_UART_LCR_DLS_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */\r
+#define ALT_UART_LCR_DLS_MSB 1\r
+/* The width in bits of the ALT_UART_LCR_DLS register field. */\r
+#define ALT_UART_LCR_DLS_WIDTH 2\r
+/* The mask used to set the ALT_UART_LCR_DLS register field value. */\r
+#define ALT_UART_LCR_DLS_SET_MSK 0x00000003\r
+/* The mask used to clear the ALT_UART_LCR_DLS register field value. */\r
+#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc\r
+/* The reset value of the ALT_UART_LCR_DLS register field. */\r
+#define ALT_UART_LCR_DLS_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_DLS field value from a register. */\r
+#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+/*\r
+ * Field : Stop Bits - stop\r
+ * \r
+ * Number of stop bits. Used to select the number of stop bits per character that\r
+ * the peripheral will transmit and receive.Note that regardless of the number of\r
+ * stop bits selected the receiver will only check the first stop bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------------|:------|:------------------------------------------\r
+ * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit \r
+ * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_STOP\r
+ * \r
+ * one stop bit\r
+ */\r
+#define ALT_UART_LCR_STOP_E_ONESTOP 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_STOP\r
+ * \r
+ * 1.5 stop bits when DLS (LCR[1:0]) is zero\r
+ */\r
+#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */\r
+#define ALT_UART_LCR_STOP_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */\r
+#define ALT_UART_LCR_STOP_MSB 2\r
+/* The width in bits of the ALT_UART_LCR_STOP register field. */\r
+#define ALT_UART_LCR_STOP_WIDTH 1\r
+/* The mask used to set the ALT_UART_LCR_STOP register field value. */\r
+#define ALT_UART_LCR_STOP_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_LCR_STOP register field value. */\r
+#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_LCR_STOP register field. */\r
+#define ALT_UART_LCR_STOP_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_STOP field value from a register. */\r
+#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Parity Enable - pen\r
+ * \r
+ * This bit is used to enable and disable parity generation and detection in a\r
+ * transmitted and received data character.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------|:------|:----------------\r
+ * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled\r
+ * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_PEN\r
+ * \r
+ * parity disabled\r
+ */\r
+#define ALT_UART_LCR_PEN_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_PEN\r
+ * \r
+ * parity enabled\r
+ */\r
+#define ALT_UART_LCR_PEN_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */\r
+#define ALT_UART_LCR_PEN_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */\r
+#define ALT_UART_LCR_PEN_MSB 3\r
+/* The width in bits of the ALT_UART_LCR_PEN register field. */\r
+#define ALT_UART_LCR_PEN_WIDTH 1\r
+/* The mask used to set the ALT_UART_LCR_PEN register field value. */\r
+#define ALT_UART_LCR_PEN_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_LCR_PEN register field value. */\r
+#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_LCR_PEN register field. */\r
+#define ALT_UART_LCR_PEN_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_PEN field value from a register. */\r
+#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Even Parity Select - eps\r
+ * \r
+ * This is used to select between even and odd parity, when parity is enabled (PEN\r
+ * set to one). If set to one, an even number of logic '1's is transmitted or\r
+ * checked. If set to zero, an odd number of logic '1's is transmitted or checked.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description\r
+ * :---------------------------|:------|:------------\r
+ * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity \r
+ * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_EPS\r
+ * \r
+ * odd parity\r
+ */\r
+#define ALT_UART_LCR_EPS_E_ODDPAR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LCR_EPS\r
+ * \r
+ * even parity\r
+ */\r
+#define ALT_UART_LCR_EPS_E_EVENPAR 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */\r
+#define ALT_UART_LCR_EPS_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */\r
+#define ALT_UART_LCR_EPS_MSB 4\r
+/* The width in bits of the ALT_UART_LCR_EPS register field. */\r
+#define ALT_UART_LCR_EPS_WIDTH 1\r
+/* The mask used to set the ALT_UART_LCR_EPS register field value. */\r
+#define ALT_UART_LCR_EPS_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_LCR_EPS register field value. */\r
+#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_LCR_EPS register field. */\r
+#define ALT_UART_LCR_EPS_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_EPS field value from a register. */\r
+#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : Break Control Bit - break\r
+ * \r
+ * This is used to cause a break condition to be transmitted to the receiving\r
+ * device. If set to one the serial output is forced to the spacing (logic 0)\r
+ * state. When not in Loopback Mode, as determined by MCR[4], the sout line is\r
+ * forced low until the Break bit is cleared. When in Loopback Mode, the break\r
+ * condition is internally looped back to the receiver and the sir_out_n line is\r
+ * forced low.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */\r
+#define ALT_UART_LCR_BREAK_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */\r
+#define ALT_UART_LCR_BREAK_MSB 6\r
+/* The width in bits of the ALT_UART_LCR_BREAK register field. */\r
+#define ALT_UART_LCR_BREAK_WIDTH 1\r
+/* The mask used to set the ALT_UART_LCR_BREAK register field value. */\r
+#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040\r
+/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */\r
+#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf\r
+/* The reset value of the ALT_UART_LCR_BREAK register field. */\r
+#define ALT_UART_LCR_BREAK_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_BREAK field value from a register. */\r
+#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+/*\r
+ * Field : Divisor Latch Access Bit - dlab\r
+ * \r
+ * Used to enable reading and writing of the Divisor Latch register (DLL and DLH)\r
+ * to set the baud rate of the UART. This bit must be cleared after initial baud\r
+ * rate setup in order to access other registers.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */\r
+#define ALT_UART_LCR_DLAB_LSB 7\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */\r
+#define ALT_UART_LCR_DLAB_MSB 7\r
+/* The width in bits of the ALT_UART_LCR_DLAB register field. */\r
+#define ALT_UART_LCR_DLAB_WIDTH 1\r
+/* The mask used to set the ALT_UART_LCR_DLAB register field value. */\r
+#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080\r
+/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */\r
+#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f\r
+/* The reset value of the ALT_UART_LCR_DLAB register field. */\r
+#define ALT_UART_LCR_DLAB_RESET 0x0\r
+/* Extracts the ALT_UART_LCR_DLAB field value from a register. */\r
+#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)\r
+/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */\r
+#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_LCR.\r
+ */\r
+struct ALT_UART_LCR_s\r
+{\r
+ uint32_t dls : 2; /* Data Length Select */\r
+ uint32_t stop : 1; /* Stop Bits */\r
+ uint32_t pen : 1; /* Parity Enable */\r
+ uint32_t eps : 1; /* Even Parity Select */\r
+ uint32_t : 1; /* *UNDEFINED* */\r
+ uint32_t break_ : 1; /* Break Control Bit */\r
+ uint32_t dlab : 1; /* Divisor Latch Access Bit */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_LCR. */\r
+typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */\r
+#define ALT_UART_LCR_OFST 0xc\r
+/* The address of the ALT_UART_LCR register. */\r
+#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST))\r
+\r
+/*\r
+ * Register : Modem Control Register - mcr\r
+ * \r
+ * Reports various operations of the modem signals\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------------------\r
+ * [0] | RW | 0x0 | Data Terminal Ready \r
+ * [1] | RW | 0x0 | Request to Send \r
+ * [2] | RW | 0x0 | Out1 \r
+ * [3] | RW | 0x0 | out2 \r
+ * [4] | RW | 0x0 | LoopBack Bit \r
+ * [5] | RW | 0x0 | Auto Flow Control Enable\r
+ * [31:6] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Data Terminal Ready - dtr\r
+ * \r
+ * This is used to directly control the Data Terminal Ready output. The value\r
+ * written to this location is inverted and driven out on uart_dtr_n, that is: The\r
+ * Data Terminal Ready output is used to inform the modem or data set that the UART\r
+ * is ready to establish communications.\r
+ * \r
+ * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is\r
+ * held inactive high while the value of this location is internally looped back\r
+ * to an input.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:---------------------------------\r
+ * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1)\r
+ * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_DTR\r
+ * \r
+ * uart_dtr_n de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MCR_DTR_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_DTR\r
+ * \r
+ * uart_dtr_n asserted (logic 0)\r
+ */\r
+#define ALT_UART_MCR_DTR_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */\r
+#define ALT_UART_MCR_DTR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */\r
+#define ALT_UART_MCR_DTR_MSB 0\r
+/* The width in bits of the ALT_UART_MCR_DTR register field. */\r
+#define ALT_UART_MCR_DTR_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_DTR register field value. */\r
+#define ALT_UART_MCR_DTR_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_MCR_DTR register field value. */\r
+#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_MCR_DTR register field. */\r
+#define ALT_UART_MCR_DTR_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_DTR field value from a register. */\r
+#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Request to Send - rts\r
+ * \r
+ * This is used to directly control the Request to Send (uart_rts_n) output. The\r
+ * Request to Send (uart_rts_n) output is used to inform the modem or data set that\r
+ * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled\r
+ * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1]\r
+ * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's\r
+ * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way,\r
+ * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is\r
+ * inactive high when above the threshold). The uart_rts_n signal will be de-\r
+ * asserted when MCR[1] is set low.\r
+ * \r
+ * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held\r
+ * inactive high while the value of this location is internally looped back to an\r
+ * input.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:---------------------------------\r
+ * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1)\r
+ * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_RTS\r
+ * \r
+ * uart_rts_n de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MCR_RTS_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_RTS\r
+ * \r
+ * uart_rts_n asserted (logic 0)\r
+ */\r
+#define ALT_UART_MCR_RTS_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */\r
+#define ALT_UART_MCR_RTS_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */\r
+#define ALT_UART_MCR_RTS_MSB 1\r
+/* The width in bits of the ALT_UART_MCR_RTS register field. */\r
+#define ALT_UART_MCR_RTS_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_RTS register field value. */\r
+#define ALT_UART_MCR_RTS_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_MCR_RTS register field value. */\r
+#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_MCR_RTS register field. */\r
+#define ALT_UART_MCR_RTS_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_RTS field value from a register. */\r
+#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Out1 - out1\r
+ * \r
+ * The value written to this location is inverted and driven out on uart_out1_n\r
+ * pin.\r
+ * \r
+ * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held\r
+ * inactive high while the value of this location is internally looped back to an\r
+ * input.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:----------------------------------\r
+ * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1)\r
+ * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_OUT1\r
+ * \r
+ * uart_out1_n de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_OUT1\r
+ * \r
+ * uart_out1_n asserted (logic 0)\r
+ */\r
+#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */\r
+#define ALT_UART_MCR_OUT1_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */\r
+#define ALT_UART_MCR_OUT1_MSB 2\r
+/* The width in bits of the ALT_UART_MCR_OUT1 register field. */\r
+#define ALT_UART_MCR_OUT1_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */\r
+#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */\r
+#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_MCR_OUT1 register field. */\r
+#define ALT_UART_MCR_OUT1_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */\r
+#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : out2 - out2\r
+ * \r
+ * This is used to directly control the user-designated uart_out2_n output. The\r
+ * value written to this location is inverted and driven out on uart_out2_n\r
+ * \r
+ * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one,\r
+ * the uart_out2_n output is held inactive high while the value of this location is\r
+ * internally looped back to an input.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:----------------------------------\r
+ * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1)\r
+ * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_OUT2\r
+ * \r
+ * uart_out2_n de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_OUT2\r
+ * \r
+ * uart_out2_n asserted (logic 0)\r
+ */\r
+#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */\r
+#define ALT_UART_MCR_OUT2_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */\r
+#define ALT_UART_MCR_OUT2_MSB 3\r
+/* The width in bits of the ALT_UART_MCR_OUT2 register field. */\r
+#define ALT_UART_MCR_OUT2_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */\r
+#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */\r
+#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_MCR_OUT2 register field. */\r
+#define ALT_UART_MCR_OUT2_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */\r
+#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : LoopBack Bit - loopback\r
+ * \r
+ * This is used to put the UART into a diagnostic mode for test purposes. If UART\r
+ * mode is NOT active, bit [6] of the modem control register MCR is set to zero,\r
+ * data on the sout line is held high, while serial data output is looped back to\r
+ * the sin line, internally. In this mode all the interrupts are fully functional.\r
+ * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n,\r
+ * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs\r
+ * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs,\r
+ * internally.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */\r
+#define ALT_UART_MCR_LOOPBACK_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */\r
+#define ALT_UART_MCR_LOOPBACK_MSB 4\r
+/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */\r
+#define ALT_UART_MCR_LOOPBACK_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */\r
+#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */\r
+#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */\r
+#define ALT_UART_MCR_LOOPBACK_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */\r
+#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : Auto Flow Control Enable - afce\r
+ * \r
+ * When FIFOs are enabled, the Auto Flow Control enable bits are active.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------|:------|:--------------------------------\r
+ * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled\r
+ * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_AFCE\r
+ * \r
+ * Auto Flow Control Mode disabled\r
+ */\r
+#define ALT_UART_MCR_AFCE_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MCR_AFCE\r
+ * \r
+ * Auto Flow Control Mode enabled\r
+ */\r
+#define ALT_UART_MCR_AFCE_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */\r
+#define ALT_UART_MCR_AFCE_LSB 5\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */\r
+#define ALT_UART_MCR_AFCE_MSB 5\r
+/* The width in bits of the ALT_UART_MCR_AFCE register field. */\r
+#define ALT_UART_MCR_AFCE_WIDTH 1\r
+/* The mask used to set the ALT_UART_MCR_AFCE register field value. */\r
+#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020\r
+/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */\r
+#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf\r
+/* The reset value of the ALT_UART_MCR_AFCE register field. */\r
+#define ALT_UART_MCR_AFCE_RESET 0x0\r
+/* Extracts the ALT_UART_MCR_AFCE field value from a register. */\r
+#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */\r
+#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_MCR.\r
+ */\r
+struct ALT_UART_MCR_s\r
+{\r
+ uint32_t dtr : 1; /* Data Terminal Ready */\r
+ uint32_t rts : 1; /* Request to Send */\r
+ uint32_t out1 : 1; /* Out1 */\r
+ uint32_t out2 : 1; /* out2 */\r
+ uint32_t loopback : 1; /* LoopBack Bit */\r
+ uint32_t afce : 1; /* Auto Flow Control Enable */\r
+ uint32_t : 26; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_MCR. */\r
+typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */\r
+#define ALT_UART_MCR_OFST 0x10\r
+/* The address of the ALT_UART_MCR register. */\r
+#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))\r
+\r
+/*\r
+ * Register : Line Status Register - lsr\r
+ * \r
+ * Reports status of transmit and receive.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:------------------------------------\r
+ * [0] | R | 0x0 | Data Ready bit \r
+ * [1] | R | 0x0 | Overrun error \r
+ * [2] | R | 0x0 | Parity Error \r
+ * [3] | R | 0x0 | Framing Error \r
+ * [4] | R | 0x0 | Break Interrupt \r
+ * [5] | R | 0x1 | Transmit Holding Register Empty bit\r
+ * [6] | R | 0x1 | Transmitter Empty bit \r
+ * [7] | R | 0x0 | Receiver FIFO Error bit \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Data Ready bit - dr\r
+ * \r
+ * This is used to indicate that the receiver contains at least one character in\r
+ * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the\r
+ * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:--------------\r
+ * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready\r
+ * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_DR\r
+ * \r
+ * no data ready\r
+ */\r
+#define ALT_UART_LSR_DR_E_NODATARDY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_DR\r
+ * \r
+ * data ready\r
+ */\r
+#define ALT_UART_LSR_DR_E_DATARDY 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */\r
+#define ALT_UART_LSR_DR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */\r
+#define ALT_UART_LSR_DR_MSB 0\r
+/* The width in bits of the ALT_UART_LSR_DR register field. */\r
+#define ALT_UART_LSR_DR_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_DR register field value. */\r
+#define ALT_UART_LSR_DR_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_LSR_DR register field value. */\r
+#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_LSR_DR register field. */\r
+#define ALT_UART_LSR_DR_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_DR field value from a register. */\r
+#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Overrun error - oe\r
+ * \r
+ * This is used to indicate the occurrence of an overrun error. This occurs if a\r
+ * new data character was received before the previous data was read. In the non-\r
+ * FIFO mode, the OE bit is set when a new character arrives in the receiver before\r
+ * the previous character was read from the RBR. When this happens, the data in the\r
+ * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is\r
+ * full and new character arrives at the receiver. The data in the FIFO is retained\r
+ * and the data in the receive shift register is lost.Reading the LSR clears the OE\r
+ * bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:-----------------\r
+ * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error\r
+ * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_OE\r
+ * \r
+ * no overrun error\r
+ */\r
+#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_OE\r
+ * \r
+ * overrun error\r
+ */\r
+#define ALT_UART_LSR_OE_E_OVERRUN 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */\r
+#define ALT_UART_LSR_OE_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */\r
+#define ALT_UART_LSR_OE_MSB 1\r
+/* The width in bits of the ALT_UART_LSR_OE register field. */\r
+#define ALT_UART_LSR_OE_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_OE register field value. */\r
+#define ALT_UART_LSR_OE_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_LSR_OE register field value. */\r
+#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_LSR_OE register field. */\r
+#define ALT_UART_LSR_OE_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_OE field value from a register. */\r
+#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Parity Error - pe\r
+ * \r
+ * This is used to indicate the occurrence of a parity error in the receiver if the\r
+ * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated\r
+ * with a character received, it is revealed when the character with the parity\r
+ * error arrives at the top of the FIFO. It should be noted that the Parity Error\r
+ * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by\r
+ * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------------|:------|:----------------\r
+ * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error\r
+ * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_PE\r
+ * \r
+ * no parity error\r
+ */\r
+#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_PE\r
+ * \r
+ * no parity error\r
+ */\r
+#define ALT_UART_LSR_PE_E_PARITYERR 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */\r
+#define ALT_UART_LSR_PE_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */\r
+#define ALT_UART_LSR_PE_MSB 2\r
+/* The width in bits of the ALT_UART_LSR_PE register field. */\r
+#define ALT_UART_LSR_PE_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_PE register field value. */\r
+#define ALT_UART_LSR_PE_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_LSR_PE register field value. */\r
+#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_LSR_PE register field. */\r
+#define ALT_UART_LSR_PE_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_PE field value from a register. */\r
+#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Framing Error - fe\r
+ * \r
+ * This is used to indicate the occurrence of a framing error in the receiver. A\r
+ * framing error occurs when the receiver does not detect a valid STOP bit in the\r
+ * received data. In the FIFO mode, since the framing error is associated with a\r
+ * character received, it is revealed when the character with the framing error is\r
+ * at the top of the FIFO. When a framing error occurs the UART will try to\r
+ * resynchronize. It does this by assuming that the error was due to the start bit\r
+ * of the next character and then continues receiving the other bit i.e. data,\r
+ * and/or parity and stop. It should be noted that the Framing Error (FE)\r
+ * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a\r
+ * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:-----------------\r
+ * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error\r
+ * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_FE\r
+ * \r
+ * no framing error\r
+ */\r
+#define ALT_UART_LSR_FE_E_NOFRMERR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_FE\r
+ * \r
+ * framing error\r
+ */\r
+#define ALT_UART_LSR_FE_E_FRMERR 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */\r
+#define ALT_UART_LSR_FE_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */\r
+#define ALT_UART_LSR_FE_MSB 3\r
+/* The width in bits of the ALT_UART_LSR_FE register field. */\r
+#define ALT_UART_LSR_FE_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_FE register field value. */\r
+#define ALT_UART_LSR_FE_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_LSR_FE register field value. */\r
+#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_LSR_FE register field. */\r
+#define ALT_UART_LSR_FE_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_FE field value from a register. */\r
+#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Break Interrupt - bi\r
+ * \r
+ * This is used to indicate the detection of a break sequence on the serial input\r
+ * data. Set whenever the serial input, sin, is held in a logic 0 state for longer\r
+ * than the sum of start time + data bits + parity + stop bits. A break condition\r
+ * on serial input causes one and only one character, consisting of all zeros, to\r
+ * be received by the UART. The character associated with the break condition is\r
+ * carried through the FIFO and is revealed when the character is at the top of the\r
+ * FIFO. Reading the LSR clears the BI bit.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */\r
+#define ALT_UART_LSR_BI_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */\r
+#define ALT_UART_LSR_BI_MSB 4\r
+/* The width in bits of the ALT_UART_LSR_BI register field. */\r
+#define ALT_UART_LSR_BI_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_BI register field value. */\r
+#define ALT_UART_LSR_BI_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_LSR_BI register field value. */\r
+#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_LSR_BI register field. */\r
+#define ALT_UART_LSR_BI_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_BI field value from a register. */\r
+#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : Transmit Holding Register Empty bit - thre\r
+ * \r
+ * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or\r
+ * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or\r
+ * Tx FIFO to the transmitter shift register and no new data has been written to\r
+ * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE\r
+ * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to\r
+ * one and FCR[0] set to one respectively), the functionality will indicate the\r
+ * transmitter FIFO is full, and no longer controls THRE interrupts, which are then\r
+ * controlled by the FCR[5:4] thresholdsetting.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */\r
+#define ALT_UART_LSR_THRE_LSB 5\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */\r
+#define ALT_UART_LSR_THRE_MSB 5\r
+/* The width in bits of the ALT_UART_LSR_THRE register field. */\r
+#define ALT_UART_LSR_THRE_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_THRE register field value. */\r
+#define ALT_UART_LSR_THRE_SET_MSK 0x00000020\r
+/* The mask used to clear the ALT_UART_LSR_THRE register field value. */\r
+#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf\r
+/* The reset value of the ALT_UART_LSR_THRE register field. */\r
+#define ALT_UART_LSR_THRE_RESET 0x1\r
+/* Extracts the ALT_UART_LSR_THRE field value from a register. */\r
+#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+/*\r
+ * Field : Transmitter Empty bit - temt\r
+ * \r
+ * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever\r
+ * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are\r
+ * disabled, this bit is set whenever the Transmitter Holding Register and the\r
+ * Transmitter Shift Register are both empty.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------|:------|:-----------------------\r
+ * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set\r
+ * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_TEMT\r
+ * \r
+ * Transmit Empty not set\r
+ */\r
+#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_TEMT\r
+ * \r
+ * Transmit Empty set\r
+ */\r
+#define ALT_UART_LSR_TEMT_E_EMPTY 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */\r
+#define ALT_UART_LSR_TEMT_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */\r
+#define ALT_UART_LSR_TEMT_MSB 6\r
+/* The width in bits of the ALT_UART_LSR_TEMT register field. */\r
+#define ALT_UART_LSR_TEMT_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_TEMT register field value. */\r
+#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040\r
+/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */\r
+#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf\r
+/* The reset value of the ALT_UART_LSR_TEMT register field. */\r
+#define ALT_UART_LSR_TEMT_RESET 0x1\r
+/* Extracts the ALT_UART_LSR_TEMT field value from a register. */\r
+#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+/*\r
+ * Field : Receiver FIFO Error bit - rfe\r
+ * \r
+ * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is\r
+ * used to indicate if there is at least one parity error, framing error, or break\r
+ * indication in the FIFO. This bit is cleared when the LSR is read and the\r
+ * character with the error is at the top of the receiver FIFO and there are no\r
+ * subsequent errors in the FIFO.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------|:------|:--------------------\r
+ * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO\r
+ * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_RFE\r
+ * \r
+ * no error in Rx FIFO\r
+ */\r
+#define ALT_UART_LSR_RFE_E_NOERR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_LSR_RFE\r
+ * \r
+ * error in Rx FIFO\r
+ */\r
+#define ALT_UART_LSR_RFE_E_ERR 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */\r
+#define ALT_UART_LSR_RFE_LSB 7\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */\r
+#define ALT_UART_LSR_RFE_MSB 7\r
+/* The width in bits of the ALT_UART_LSR_RFE register field. */\r
+#define ALT_UART_LSR_RFE_WIDTH 1\r
+/* The mask used to set the ALT_UART_LSR_RFE register field value. */\r
+#define ALT_UART_LSR_RFE_SET_MSK 0x00000080\r
+/* The mask used to clear the ALT_UART_LSR_RFE register field value. */\r
+#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f\r
+/* The reset value of the ALT_UART_LSR_RFE register field. */\r
+#define ALT_UART_LSR_RFE_RESET 0x0\r
+/* Extracts the ALT_UART_LSR_RFE field value from a register. */\r
+#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)\r
+/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */\r
+#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_LSR.\r
+ */\r
+struct ALT_UART_LSR_s\r
+{\r
+ const uint32_t dr : 1; /* Data Ready bit */\r
+ const uint32_t oe : 1; /* Overrun error */\r
+ const uint32_t pe : 1; /* Parity Error */\r
+ const uint32_t fe : 1; /* Framing Error */\r
+ const uint32_t bi : 1; /* Break Interrupt */\r
+ const uint32_t thre : 1; /* Transmit Holding Register Empty bit */\r
+ const uint32_t temt : 1; /* Transmitter Empty bit */\r
+ const uint32_t rfe : 1; /* Receiver FIFO Error bit */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_LSR. */\r
+typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */\r
+#define ALT_UART_LSR_OFST 0x14\r
+/* The address of the ALT_UART_LSR register. */\r
+#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST))\r
+\r
+/*\r
+ * Register : Modem Status Register - msr\r
+ * \r
+ * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to\r
+ * indicate a change on the modem control inputs, a modem status interrupt will be\r
+ * generated if enabled via the IER regardless of when the change occurred. Since\r
+ * the delta bits (bits 0, 1, 3) can get set after a reset if their respective\r
+ * modem signals are active (see individual bits for details), a read of the MSR\r
+ * after reset can be performed to prevent unwanted interrupts.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------------------\r
+ * [0] | R | 0x0 | Delta Clear to Send \r
+ * [1] | R | 0x0 | Delta Data Set Ready \r
+ * [2] | R | 0x0 | Trailing Edge of Ring Indicator\r
+ * [3] | R | 0x0 | Delta Data Carrier Detect \r
+ * [4] | R | 0x0 | Clear to Send \r
+ * [5] | R | 0x0 | Data Set Ready \r
+ * [6] | R | 0x0 | Ring Indicator \r
+ * [7] | R | 0x0 | Data Carrier Detect \r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Delta Clear to Send - dcts\r
+ * \r
+ * This is used to indicate that the modem control line uart_cts_n has changed\r
+ * since the last time the MSR was read. That is: Reading the MSR clears the DCTS\r
+ * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit\r
+ * [1] RTS of register MCR.\r
+ * \r
+ * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and\r
+ * a reset occurs (software or otherwise), then the DCTS bit will get set when the\r
+ * reset is removed if the uart_cts_n signal remains asserted.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:-----------------------------------------------\r
+ * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR\r
+ * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DCTS\r
+ * \r
+ * no change on uart_cts_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DCTS_E_NOCHG 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DCTS\r
+ * \r
+ * change on uart_cts_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DCTS_E_CHG 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */\r
+#define ALT_UART_MSR_DCTS_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */\r
+#define ALT_UART_MSR_DCTS_MSB 0\r
+/* The width in bits of the ALT_UART_MSR_DCTS register field. */\r
+#define ALT_UART_MSR_DCTS_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_DCTS register field value. */\r
+#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */\r
+#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_MSR_DCTS register field. */\r
+#define ALT_UART_MSR_DCTS_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_DCTS field value from a register. */\r
+#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Delta Data Set Ready - ddsr\r
+ * \r
+ * This is used to indicate that the modem control line uart_dsr_n has changed\r
+ * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In\r
+ * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of\r
+ * register MCR .\r
+ * \r
+ * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and\r
+ * a reset occurs (software or otherwise), then the DDSR bit will get set when the\r
+ * reset is removed if the uart_dsr_n signal remains asserted.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:-----------------------------------------------\r
+ * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR\r
+ * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DDSR\r
+ * \r
+ * no change on uart_dsr_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DDSR_E_NOCHG 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DDSR\r
+ * \r
+ * change on uart_dsr_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DDSR_E_CHG 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */\r
+#define ALT_UART_MSR_DDSR_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */\r
+#define ALT_UART_MSR_DDSR_MSB 1\r
+/* The width in bits of the ALT_UART_MSR_DDSR register field. */\r
+#define ALT_UART_MSR_DDSR_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_DDSR register field value. */\r
+#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */\r
+#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_MSR_DDSR register field. */\r
+#define ALT_UART_MSR_DDSR_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_DDSR field value from a register. */\r
+#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Trailing Edge of Ring Indicator - teri\r
+ * \r
+ * This is used to indicate that a change on the input uart_ri_n (from an active\r
+ * low, to an inactive high state) has occurred since the last time the MSR was\r
+ * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register\r
+ * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state\r
+ * from a high to a low.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:----------------------------------------------\r
+ * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR\r
+ * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_TERI\r
+ * \r
+ * no change on uart_ri_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_TERI_E_NOCHG 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_TERI\r
+ * \r
+ * change on uart_ri_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_TERI_E_CHG 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */\r
+#define ALT_UART_MSR_TERI_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */\r
+#define ALT_UART_MSR_TERI_MSB 2\r
+/* The width in bits of the ALT_UART_MSR_TERI register field. */\r
+#define ALT_UART_MSR_TERI_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_TERI register field value. */\r
+#define ALT_UART_MSR_TERI_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_MSR_TERI register field value. */\r
+#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_MSR_TERI register field. */\r
+#define ALT_UART_MSR_TERI_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_TERI field value from a register. */\r
+#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Delta Data Carrier Detect - ddcd\r
+ * \r
+ * This is used to indicate that the modem control line dcd_n has changed since the\r
+ * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback\r
+ * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3]\r
+ * uart_out2 of register MCR.\r
+ * \r
+ * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and\r
+ * a reset occurs (software or otherwise), then the DDCD bit will get set when the\r
+ * reset is removed if the uart_dcd_n signal remains asserted.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:-----------------------------------------------\r
+ * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR\r
+ * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DDCD\r
+ * \r
+ * no change on uart_dcd_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DDCD_E_NOCHG 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DDCD\r
+ * \r
+ * change on uart_dcd_n since last read of MSR\r
+ */\r
+#define ALT_UART_MSR_DDCD_E_CHG 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */\r
+#define ALT_UART_MSR_DDCD_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */\r
+#define ALT_UART_MSR_DDCD_MSB 3\r
+/* The width in bits of the ALT_UART_MSR_DDCD register field. */\r
+#define ALT_UART_MSR_DDCD_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_DDCD register field value. */\r
+#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */\r
+#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_MSR_DDCD register field. */\r
+#define ALT_UART_MSR_DDCD_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_DDCD field value from a register. */\r
+#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Clear to Send - cts\r
+ * \r
+ * This is used to indicate the current state of the modem control line uart_cts_n.\r
+ * That is, this bit is the complement uart_cts_n. When the Clear to Send input\r
+ * (uart_cts_n) is asserted it is an indication that the modem or data set is ready\r
+ * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set\r
+ * to one, CTS is the same as bit [1] RTS of register MCR.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:------------------------------------------\r
+ * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1)\r
+ * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_CTS\r
+ * \r
+ * uart_cts_n input is de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MSR_CTS_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_CTS\r
+ * \r
+ * uart_cts_n input is asserted (logic 0)\r
+ */\r
+#define ALT_UART_MSR_CTS_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */\r
+#define ALT_UART_MSR_CTS_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */\r
+#define ALT_UART_MSR_CTS_MSB 4\r
+/* The width in bits of the ALT_UART_MSR_CTS register field. */\r
+#define ALT_UART_MSR_CTS_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_CTS register field value. */\r
+#define ALT_UART_MSR_CTS_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_MSR_CTS register field value. */\r
+#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_MSR_CTS register field. */\r
+#define ALT_UART_MSR_CTS_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_CTS field value from a register. */\r
+#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : Data Set Ready - dsr\r
+ * \r
+ * This is used to indicate the current state of the modem control line uart_dsr_n.\r
+ * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input\r
+ * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready\r
+ * to establish communications with the uart. In Loopback Mode bit [4] of register\r
+ * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:------------------------------------------\r
+ * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1)\r
+ * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DSR\r
+ * \r
+ * uart_dsr_n input is de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MSR_DSR_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DSR\r
+ * \r
+ * uart_dsr_n input is asserted (logic 0)\r
+ */\r
+#define ALT_UART_MSR_DSR_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */\r
+#define ALT_UART_MSR_DSR_LSB 5\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */\r
+#define ALT_UART_MSR_DSR_MSB 5\r
+/* The width in bits of the ALT_UART_MSR_DSR register field. */\r
+#define ALT_UART_MSR_DSR_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_DSR register field value. */\r
+#define ALT_UART_MSR_DSR_SET_MSK 0x00000020\r
+/* The mask used to clear the ALT_UART_MSR_DSR register field value. */\r
+#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf\r
+/* The reset value of the ALT_UART_MSR_DSR register field. */\r
+#define ALT_UART_MSR_DSR_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_DSR field value from a register. */\r
+#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+/*\r
+ * Field : Ring Indicator - ri\r
+ * \r
+ * This bit is used to indicate the current state of the modem control line\r
+ * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator\r
+ * input (uart_ri_n) is asserted it is an indication that a telephone ringing\r
+ * signal has been received by the modem or data set. In Loopback Mode bit [4] of\r
+ * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------|:------|:-----------------------------------------\r
+ * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1)\r
+ * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_RI\r
+ * \r
+ * uart_ri_n input is de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MSR_RI_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_RI\r
+ * \r
+ * uart_ri_n input is asserted (logic 0)\r
+ */\r
+#define ALT_UART_MSR_RI_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */\r
+#define ALT_UART_MSR_RI_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */\r
+#define ALT_UART_MSR_RI_MSB 6\r
+/* The width in bits of the ALT_UART_MSR_RI register field. */\r
+#define ALT_UART_MSR_RI_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_RI register field value. */\r
+#define ALT_UART_MSR_RI_SET_MSK 0x00000040\r
+/* The mask used to clear the ALT_UART_MSR_RI register field value. */\r
+#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf\r
+/* The reset value of the ALT_UART_MSR_RI register field. */\r
+#define ALT_UART_MSR_RI_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_RI field value from a register. */\r
+#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+/*\r
+ * Field : Data Carrier Detect - dcd\r
+ * \r
+ * This is used to indicate the current state of the modem control line uart_dcd_n.\r
+ * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect\r
+ * input (uart_dcd_n) is asserted it is an indication that the carrier has been\r
+ * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is\r
+ * the same as MCR[3] (uart_out2).\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:------------------------------------------\r
+ * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1)\r
+ * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0) \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DCD\r
+ * \r
+ * uart_dcd_n input is de-asserted (logic 1)\r
+ */\r
+#define ALT_UART_MSR_DCD_E_LOGIC1 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_MSR_DCD\r
+ * \r
+ * uart_dcd_n input is asserted (logic 0)\r
+ */\r
+#define ALT_UART_MSR_DCD_E_LOGIC0 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */\r
+#define ALT_UART_MSR_DCD_LSB 7\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */\r
+#define ALT_UART_MSR_DCD_MSB 7\r
+/* The width in bits of the ALT_UART_MSR_DCD register field. */\r
+#define ALT_UART_MSR_DCD_WIDTH 1\r
+/* The mask used to set the ALT_UART_MSR_DCD register field value. */\r
+#define ALT_UART_MSR_DCD_SET_MSK 0x00000080\r
+/* The mask used to clear the ALT_UART_MSR_DCD register field value. */\r
+#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f\r
+/* The reset value of the ALT_UART_MSR_DCD register field. */\r
+#define ALT_UART_MSR_DCD_RESET 0x0\r
+/* Extracts the ALT_UART_MSR_DCD field value from a register. */\r
+#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)\r
+/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */\r
+#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_MSR.\r
+ */\r
+struct ALT_UART_MSR_s\r
+{\r
+ const uint32_t dcts : 1; /* Delta Clear to Send */\r
+ const uint32_t ddsr : 1; /* Delta Data Set Ready */\r
+ const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */\r
+ const uint32_t ddcd : 1; /* Delta Data Carrier Detect */\r
+ const uint32_t cts : 1; /* Clear to Send */\r
+ const uint32_t dsr : 1; /* Data Set Ready */\r
+ const uint32_t ri : 1; /* Ring Indicator */\r
+ const uint32_t dcd : 1; /* Data Carrier Detect */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_MSR. */\r
+typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */\r
+#define ALT_UART_MSR_OFST 0x18\r
+/* The address of the ALT_UART_MSR register. */\r
+#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST))\r
+\r
+/*\r
+ * Register : Scratchpad Register - scr\r
+ * \r
+ * Scratchpad Register\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------\r
+ * [7:0] | RW | 0x0 | Scratchpad Register\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Scratchpad Register - scr\r
+ * \r
+ * This register is for programmers to use as a temporary storage space.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */\r
+#define ALT_UART_SCR_SCR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */\r
+#define ALT_UART_SCR_SCR_MSB 7\r
+/* The width in bits of the ALT_UART_SCR_SCR register field. */\r
+#define ALT_UART_SCR_SCR_WIDTH 8\r
+/* The mask used to set the ALT_UART_SCR_SCR register field value. */\r
+#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_SCR_SCR register field value. */\r
+#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_SCR_SCR register field. */\r
+#define ALT_UART_SCR_SCR_RESET 0x0\r
+/* Extracts the ALT_UART_SCR_SCR field value from a register. */\r
+#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */\r
+#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SCR.\r
+ */\r
+struct ALT_UART_SCR_s\r
+{\r
+ uint32_t scr : 8; /* Scratchpad Register */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SCR. */\r
+typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */\r
+#define ALT_UART_SCR_OFST 0x1c\r
+/* The address of the ALT_UART_SCR register. */\r
+#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST))\r
+\r
+/*\r
+ * Register : Shadow Receive Buffer Register - srbr\r
+ * \r
+ * Used to accomadate burst accesses from the master.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:----------------------\r
+ * [7:0] | RW | 0x0 | Shadow Receive Buffer\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Receive Buffer - srbr\r
+ * \r
+ * This is a shadow register for the RBR and has been allocated one 32-bit location\r
+ * so as to accommodate burst accesses from the master.This register contains the\r
+ * data byte received on the serial input port (sin). The data in this register is\r
+ * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.\r
+ * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR\r
+ * must be read before the next data arrives, otherwise it will be overwritten,\r
+ * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this\r
+ * register accesses the head of the receive FIFO. If the receive FIFO is full and\r
+ * this register is not read before the next data character arrives, then the data\r
+ * already in the FIFO will be preserved but any incoming data will be lost. An\r
+ * overrun error will also occur.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */\r
+#define ALT_UART_SRBR_SRBR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */\r
+#define ALT_UART_SRBR_SRBR_MSB 7\r
+/* The width in bits of the ALT_UART_SRBR_SRBR register field. */\r
+#define ALT_UART_SRBR_SRBR_WIDTH 8\r
+/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */\r
+#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */\r
+#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_SRBR_SRBR register field. */\r
+#define ALT_UART_SRBR_SRBR_RESET 0x0\r
+/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */\r
+#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */\r
+#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SRBR.\r
+ */\r
+struct ALT_UART_SRBR_s\r
+{\r
+ uint32_t srbr : 8; /* Shadow Receive Buffer */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SRBR. */\r
+typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */\r
+#define ALT_UART_SRBR_OFST 0x30\r
+/* The address of the ALT_UART_SRBR register. */\r
+#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))\r
+\r
+/*\r
+ * Register : Shadow Transmit Buffer Register - sthr\r
+ * \r
+ * Used to accomadate burst accesses from the master.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-----------------------\r
+ * [7:0] | RW | 0x0 | Shadow Transmit Buffer\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Transmit Buffer - sthr\r
+ * \r
+ * This is a shadow register for the THR and has been allocated sixteen 32-bit\r
+ * locations so as to accommodate burst accesses from the master. This register\r
+ * contains data to be transmitted on the serial output port (sout). Data should\r
+ * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If\r
+ * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing\r
+ * a single character to the THR clears the THRE. Any additional writes to the THR\r
+ * before the THRE is set again causes the THR data to be overwritten. If FIFO's\r
+ * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters\r
+ * of data may be written to the THR before the FIFO is full. The UART FIFO depth\r
+ * is configured for 128 characters. Any attempt to write data when the FIFO is\r
+ * full results in the write data being lost.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */\r
+#define ALT_UART_STHR_STHR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */\r
+#define ALT_UART_STHR_STHR_MSB 7\r
+/* The width in bits of the ALT_UART_STHR_STHR register field. */\r
+#define ALT_UART_STHR_STHR_WIDTH 8\r
+/* The mask used to set the ALT_UART_STHR_STHR register field value. */\r
+#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_STHR_STHR register field value. */\r
+#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_STHR_STHR register field. */\r
+#define ALT_UART_STHR_STHR_RESET 0x0\r
+/* Extracts the ALT_UART_STHR_STHR field value from a register. */\r
+#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */\r
+#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_STHR.\r
+ */\r
+struct ALT_UART_STHR_s\r
+{\r
+ uint32_t sthr : 8; /* Shadow Transmit Buffer */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_STHR. */\r
+typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */\r
+#define ALT_UART_STHR_OFST 0x34\r
+/* The address of the ALT_UART_STHR register. */\r
+#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST))\r
+\r
+/*\r
+ * Register : FIFO Access Register - far\r
+ * \r
+ * This register is used in FIFO access testing.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:----------------\r
+ * [0] | RW | 0x0 | FIFO ACCESS Bit\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : FIFO ACCESS Bit - srbr_sthr\r
+ * \r
+ * This register is used to enable a FIFO access mode for testing, so that the\r
+ * receive FIFO can be written by the master and the transmit FIFO can be read by\r
+ * the master when FIFO's are enabled. When FIFO's are not enabled it allows the\r
+ * RBR to be written by the master and the THR to be read by the master\r
+ * \r
+ * Note: That when the FIFO access mode is enabled/disabled, the control portion of\r
+ * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------------|:------|:--------------------------\r
+ * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled\r
+ * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_FAR_SRBR_STHR\r
+ * \r
+ * FIFO access mode disabled\r
+ */\r
+#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_FAR_SRBR_STHR\r
+ * \r
+ * FIFO access mode enabled\r
+ */\r
+#define ALT_UART_FAR_SRBR_STHR_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */\r
+#define ALT_UART_FAR_SRBR_STHR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */\r
+#define ALT_UART_FAR_SRBR_STHR_MSB 0\r
+/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */\r
+#define ALT_UART_FAR_SRBR_STHR_WIDTH 1\r
+/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */\r
+#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */\r
+#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */\r
+#define ALT_UART_FAR_SRBR_STHR_RESET 0x0\r
+/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */\r
+#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */\r
+#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_FAR.\r
+ */\r
+struct ALT_UART_FAR_s\r
+{\r
+ uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_FAR. */\r
+typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */\r
+#define ALT_UART_FAR_OFST 0x70\r
+/* The address of the ALT_UART_FAR register. */\r
+#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST))\r
+\r
+/*\r
+ * Register : Transmit FIFO Read Register - tfr\r
+ * \r
+ * Used in FIFO Access test mode.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------------\r
+ * [7:0] | R | 0x0 | Transmit FIFO Read\r
+ * [31:8] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Transmit FIFO Read - tfr\r
+ * \r
+ * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to\r
+ * one). When FIFO's are enabled, reading this register gives the data at the top\r
+ * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the\r
+ * next data value that is currently at the top of the FIFO. When FIFO's are not\r
+ * enabled, reading this register gives the data in the THR.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */\r
+#define ALT_UART_TFR_TFR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */\r
+#define ALT_UART_TFR_TFR_MSB 7\r
+/* The width in bits of the ALT_UART_TFR_TFR register field. */\r
+#define ALT_UART_TFR_TFR_WIDTH 8\r
+/* The mask used to set the ALT_UART_TFR_TFR register field value. */\r
+#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_TFR_TFR register field value. */\r
+#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_TFR_TFR register field. */\r
+#define ALT_UART_TFR_TFR_RESET 0x0\r
+/* Extracts the ALT_UART_TFR_TFR field value from a register. */\r
+#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */\r
+#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_TFR.\r
+ */\r
+struct ALT_UART_TFR_s\r
+{\r
+ const uint32_t tfr : 8; /* Transmit FIFO Read */\r
+ uint32_t : 24; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_TFR. */\r
+typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */\r
+#define ALT_UART_TFR_OFST 0x74\r
+/* The address of the ALT_UART_TFR register. */\r
+#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST))\r
+\r
+/*\r
+ * Register : Receive FIFO Write - RFW\r
+ * \r
+ * Used only with FIFO access test mode.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :--------|:-------|:------|:---------------------------\r
+ * [7:0] | W | 0x0 | Receive FIFO Write Field \r
+ * [8] | W | 0x0 | Receive FIFO Parity Error \r
+ * [9] | W | 0x0 | Receive FIFO Framing Error\r
+ * [31:10] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Receive FIFO Write Field - rfwd\r
+ * \r
+ * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to\r
+ * one). When FIFO's are enabled, the data that is written to the RFWD is pushed\r
+ * into the receive FIFO. Each consecutive write pushes the new data to the next\r
+ * write location in the receive FIFO. When FIFO's are not enabled, the data that\r
+ * is written to the RFWD is pushed into the RBR.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */\r
+#define ALT_UART_RFW_RFWD_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */\r
+#define ALT_UART_RFW_RFWD_MSB 7\r
+/* The width in bits of the ALT_UART_RFW_RFWD register field. */\r
+#define ALT_UART_RFW_RFWD_WIDTH 8\r
+/* The mask used to set the ALT_UART_RFW_RFWD register field value. */\r
+#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff\r
+/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */\r
+#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00\r
+/* The reset value of the ALT_UART_RFW_RFWD register field. */\r
+#define ALT_UART_RFW_RFWD_RESET 0x0\r
+/* Extracts the ALT_UART_RFW_RFWD field value from a register. */\r
+#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)\r
+/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */\r
+#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)\r
+\r
+/*\r
+ * Field : Receive FIFO Parity Error - rfpe\r
+ * \r
+ * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to\r
+ * one). When FIFO's are enabled, this bit is used to write parity error detection\r
+ * information to the receive FIFO. When FIFO's are not enabled, this bit is used\r
+ * to write parity error detection information to the RBR.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */\r
+#define ALT_UART_RFW_RFPE_LSB 8\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */\r
+#define ALT_UART_RFW_RFPE_MSB 8\r
+/* The width in bits of the ALT_UART_RFW_RFPE register field. */\r
+#define ALT_UART_RFW_RFPE_WIDTH 1\r
+/* The mask used to set the ALT_UART_RFW_RFPE register field value. */\r
+#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100\r
+/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */\r
+#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff\r
+/* The reset value of the ALT_UART_RFW_RFPE register field. */\r
+#define ALT_UART_RFW_RFPE_RESET 0x0\r
+/* Extracts the ALT_UART_RFW_RFPE field value from a register. */\r
+#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)\r
+/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */\r
+#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)\r
+\r
+/*\r
+ * Field : Receive FIFO Framing Error - RFFE\r
+ * \r
+ * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to\r
+ * one). When FIFO's are enabled, this bit is used to write framing error detection\r
+ * information to the receive FIFO. When FIFO's are not enabled, this bit is used\r
+ * to write framing error detection information to the RBR.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */\r
+#define ALT_UART_RFW_RFFE_LSB 9\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */\r
+#define ALT_UART_RFW_RFFE_MSB 9\r
+/* The width in bits of the ALT_UART_RFW_RFFE register field. */\r
+#define ALT_UART_RFW_RFFE_WIDTH 1\r
+/* The mask used to set the ALT_UART_RFW_RFFE register field value. */\r
+#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200\r
+/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */\r
+#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff\r
+/* The reset value of the ALT_UART_RFW_RFFE register field. */\r
+#define ALT_UART_RFW_RFFE_RESET 0x0\r
+/* Extracts the ALT_UART_RFW_RFFE field value from a register. */\r
+#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)\r
+/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */\r
+#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_RFW.\r
+ */\r
+struct ALT_UART_RFW_s\r
+{\r
+ uint32_t rfwd : 8; /* Receive FIFO Write Field */\r
+ uint32_t rfpe : 1; /* Receive FIFO Parity Error */\r
+ uint32_t RFFE : 1; /* Receive FIFO Framing Error */\r
+ uint32_t : 22; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_RFW. */\r
+typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */\r
+#define ALT_UART_RFW_OFST 0x78\r
+/* The address of the ALT_UART_RFW register. */\r
+#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST))\r
+\r
+/*\r
+ * Register : UART Status Register - usr\r
+ * \r
+ * Status of FIFO Operations.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-----------------------\r
+ * [0] | ??? | 0x0 | *UNDEFINED* \r
+ * [1] | R | 0x1 | Transmit FIFO Not Full\r
+ * [2] | R | 0x1 | Transmit FIFO Empty \r
+ * [3] | R | 0x0 | Receive FIFO Not Empty\r
+ * [4] | R | 0x0 | Receive FIFO Full \r
+ * [31:5] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Transmit FIFO Not Full - tfnf\r
+ * \r
+ * This Bit is used to indicate that the transmit FIFO in not full. This bit is\r
+ * cleared when the Tx FIFO is full.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:--------------------------\r
+ * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full \r
+ * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_TFNF\r
+ * \r
+ * Transmit FIFO is full\r
+ */\r
+#define ALT_UART_USR_TFNF_E_FULL 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_TFNF\r
+ * \r
+ * Transmit FIFO is not full\r
+ */\r
+#define ALT_UART_USR_TFNF_E_NOTFULL 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */\r
+#define ALT_UART_USR_TFNF_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */\r
+#define ALT_UART_USR_TFNF_MSB 1\r
+/* The width in bits of the ALT_UART_USR_TFNF register field. */\r
+#define ALT_UART_USR_TFNF_WIDTH 1\r
+/* The mask used to set the ALT_UART_USR_TFNF register field value. */\r
+#define ALT_UART_USR_TFNF_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_USR_TFNF register field value. */\r
+#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_USR_TFNF register field. */\r
+#define ALT_UART_USR_TFNF_RESET 0x1\r
+/* Extracts the ALT_UART_USR_TFNF field value from a register. */\r
+#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */\r
+#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Transmit FIFO Empty - tfe\r
+ * \r
+ * This is used to indicate that the transmit FIFO is completely empty. This bit is\r
+ * cleared when the Tx FIFO is no longer empty.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:---------------------------\r
+ * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty\r
+ * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_TFE\r
+ * \r
+ * Transmit FIFO is not empty\r
+ */\r
+#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_TFE\r
+ * \r
+ * Transmit FIFO is empty\r
+ */\r
+#define ALT_UART_USR_TFE_E_EMPTY 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */\r
+#define ALT_UART_USR_TFE_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */\r
+#define ALT_UART_USR_TFE_MSB 2\r
+/* The width in bits of the ALT_UART_USR_TFE register field. */\r
+#define ALT_UART_USR_TFE_WIDTH 1\r
+/* The mask used to set the ALT_UART_USR_TFE register field value. */\r
+#define ALT_UART_USR_TFE_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_USR_TFE register field value. */\r
+#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_USR_TFE register field. */\r
+#define ALT_UART_USR_TFE_RESET 0x1\r
+/* Extracts the ALT_UART_USR_TFE field value from a register. */\r
+#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */\r
+#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+/*\r
+ * Field : Receive FIFO Not Empty - rfne\r
+ * \r
+ * This Bit is used to indicate that the receive FIFO contains one or more entries.\r
+ * This bit is cleared when the Rx FIFO is empty.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------|:------|:--------------------------\r
+ * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty \r
+ * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_RFNE\r
+ * \r
+ * Receiive FIFO is empty\r
+ */\r
+#define ALT_UART_USR_RFNE_E_EMPTY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_RFNE\r
+ * \r
+ * Receive FIFO is not empty\r
+ */\r
+#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */\r
+#define ALT_UART_USR_RFNE_LSB 3\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */\r
+#define ALT_UART_USR_RFNE_MSB 3\r
+/* The width in bits of the ALT_UART_USR_RFNE register field. */\r
+#define ALT_UART_USR_RFNE_WIDTH 1\r
+/* The mask used to set the ALT_UART_USR_RFNE register field value. */\r
+#define ALT_UART_USR_RFNE_SET_MSK 0x00000008\r
+/* The mask used to clear the ALT_UART_USR_RFNE register field value. */\r
+#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7\r
+/* The reset value of the ALT_UART_USR_RFNE register field. */\r
+#define ALT_UART_USR_RFNE_RESET 0x0\r
+/* Extracts the ALT_UART_USR_RFNE field value from a register. */\r
+#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)\r
+/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */\r
+#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)\r
+\r
+/*\r
+ * Field : Receive FIFO Full - rff\r
+ * \r
+ * This Bit is used to indicate that the receive FIFO is completely full. This bit\r
+ * is cleared when the Rx FIFO is no longer full.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------|:------|:-----------------------\r
+ * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full\r
+ * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_RFF\r
+ * \r
+ * Receiive FIFO not full\r
+ */\r
+#define ALT_UART_USR_RFF_E_NOTFULL 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_USR_RFF\r
+ * \r
+ * Transmit FIFO is full\r
+ */\r
+#define ALT_UART_USR_RFF_E_FULL 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */\r
+#define ALT_UART_USR_RFF_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */\r
+#define ALT_UART_USR_RFF_MSB 4\r
+/* The width in bits of the ALT_UART_USR_RFF register field. */\r
+#define ALT_UART_USR_RFF_WIDTH 1\r
+/* The mask used to set the ALT_UART_USR_RFF register field value. */\r
+#define ALT_UART_USR_RFF_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_USR_RFF register field value. */\r
+#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_USR_RFF register field. */\r
+#define ALT_UART_USR_RFF_RESET 0x0\r
+/* Extracts the ALT_UART_USR_RFF field value from a register. */\r
+#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */\r
+#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_USR.\r
+ */\r
+struct ALT_UART_USR_s\r
+{\r
+ uint32_t : 1; /* *UNDEFINED* */\r
+ const uint32_t tfnf : 1; /* Transmit FIFO Not Full */\r
+ const uint32_t tfe : 1; /* Transmit FIFO Empty */\r
+ const uint32_t rfne : 1; /* Receive FIFO Not Empty */\r
+ const uint32_t rff : 1; /* Receive FIFO Full */\r
+ uint32_t : 27; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_USR. */\r
+typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_USR register from the beginning of the component. */\r
+#define ALT_UART_USR_OFST 0x7c\r
+/* The address of the ALT_UART_USR register. */\r
+#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST))\r
+\r
+/*\r
+ * Register : Transmit FIFO Level - tfl\r
+ * \r
+ * This register is used to specify the number of data entries in the Tx FIFO.\r
+ * Status Bits in USR register monitor the FIFO state.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------\r
+ * [4:0] | R | 0x0 | Transmit FIFO Level\r
+ * [31:5] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Transmit FIFO Level - tfl\r
+ * \r
+ * This indicates the number of data entries in the transmit FIFO.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */\r
+#define ALT_UART_TFL_TFL_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */\r
+#define ALT_UART_TFL_TFL_MSB 4\r
+/* The width in bits of the ALT_UART_TFL_TFL register field. */\r
+#define ALT_UART_TFL_TFL_WIDTH 5\r
+/* The mask used to set the ALT_UART_TFL_TFL register field value. */\r
+#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f\r
+/* The mask used to clear the ALT_UART_TFL_TFL register field value. */\r
+#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0\r
+/* The reset value of the ALT_UART_TFL_TFL register field. */\r
+#define ALT_UART_TFL_TFL_RESET 0x0\r
+/* Extracts the ALT_UART_TFL_TFL field value from a register. */\r
+#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0)\r
+/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */\r
+#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_TFL.\r
+ */\r
+struct ALT_UART_TFL_s\r
+{\r
+ const uint32_t tfl : 5; /* Transmit FIFO Level */\r
+ uint32_t : 27; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_TFL. */\r
+typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */\r
+#define ALT_UART_TFL_OFST 0x80\r
+/* The address of the ALT_UART_TFL register. */\r
+#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST))\r
+\r
+/*\r
+ * Register : Receive FIFO Level Write - rfl\r
+ * \r
+ * This register is used to specify the number of data entries in the Tx FIFO.\r
+ * Status Bits in USR register monitor the FIFO state.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------------------\r
+ * [4:0] | R | 0x0 | Receive FIFO Level Status\r
+ * [31:5] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Receive FIFO Level Status - rfl\r
+ * \r
+ * This indicates the number of data entries in the receive FIFO.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */\r
+#define ALT_UART_RFL_RFL_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */\r
+#define ALT_UART_RFL_RFL_MSB 4\r
+/* The width in bits of the ALT_UART_RFL_RFL register field. */\r
+#define ALT_UART_RFL_RFL_WIDTH 5\r
+/* The mask used to set the ALT_UART_RFL_RFL register field value. */\r
+#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f\r
+/* The mask used to clear the ALT_UART_RFL_RFL register field value. */\r
+#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0\r
+/* The reset value of the ALT_UART_RFL_RFL register field. */\r
+#define ALT_UART_RFL_RFL_RESET 0x0\r
+/* Extracts the ALT_UART_RFL_RFL field value from a register. */\r
+#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0)\r
+/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */\r
+#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_RFL.\r
+ */\r
+struct ALT_UART_RFL_s\r
+{\r
+ const uint32_t rfl : 5; /* Receive FIFO Level Status */\r
+ uint32_t : 27; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_RFL. */\r
+typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */\r
+#define ALT_UART_RFL_OFST 0x84\r
+/* The address of the ALT_UART_RFL register. */\r
+#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST))\r
+\r
+/*\r
+ * Register : Software Reset Register - srr\r
+ * \r
+ * Provides Software Resets for Tx/Rx FIFO's and the uart.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:--------------\r
+ * [0] | W | 0x0 | UART Reset \r
+ * [1] | W | 0x0 | Rx FIFO Reset\r
+ * [2] | W | 0x0 | Tx FIFO Reset\r
+ * [31:3] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : UART Reset - ur\r
+ * \r
+ * This asynchronously resets the UART and synchronously removes the reset\r
+ * assertion.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------|:------|:--------------\r
+ * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart\r
+ * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_UR\r
+ * \r
+ * No reset Uart\r
+ */\r
+#define ALT_UART_SRR_UR_E_NORST 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_UR\r
+ * \r
+ * Reset Uart\r
+ */\r
+#define ALT_UART_SRR_UR_E_RST 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */\r
+#define ALT_UART_SRR_UR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */\r
+#define ALT_UART_SRR_UR_MSB 0\r
+/* The width in bits of the ALT_UART_SRR_UR register field. */\r
+#define ALT_UART_SRR_UR_WIDTH 1\r
+/* The mask used to set the ALT_UART_SRR_UR register field value. */\r
+#define ALT_UART_SRR_UR_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_SRR_UR register field value. */\r
+#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_SRR_UR register field. */\r
+#define ALT_UART_SRR_UR_RESET 0x0\r
+/* Extracts the ALT_UART_SRR_UR field value from a register. */\r
+#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */\r
+#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+/*\r
+ * Field : Rx FIFO Reset - rfr\r
+ * \r
+ * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used\r
+ * to remove the burden on software having to store previously written FCR values\r
+ * (which are pretty static) just to reset the receive FIFO. This resets the\r
+ * control portion of the receive FIFO and treats the FIFO as empty. This will also\r
+ * de-assert the DMA Rx request and single signals. Note that this bit is 'self-\r
+ * clearing' and it is not necessary to clear this bit.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------|:------|:-----------------\r
+ * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO\r
+ * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_RFR\r
+ * \r
+ * No reset Rx FIFO\r
+ */\r
+#define ALT_UART_SRR_RFR_E_NORST 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_RFR\r
+ * \r
+ * Reset Rx FIFO\r
+ */\r
+#define ALT_UART_SRR_RFR_E_RST 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */\r
+#define ALT_UART_SRR_RFR_LSB 1\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */\r
+#define ALT_UART_SRR_RFR_MSB 1\r
+/* The width in bits of the ALT_UART_SRR_RFR register field. */\r
+#define ALT_UART_SRR_RFR_WIDTH 1\r
+/* The mask used to set the ALT_UART_SRR_RFR register field value. */\r
+#define ALT_UART_SRR_RFR_SET_MSK 0x00000002\r
+/* The mask used to clear the ALT_UART_SRR_RFR register field value. */\r
+#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd\r
+/* The reset value of the ALT_UART_SRR_RFR register field. */\r
+#define ALT_UART_SRR_RFR_RESET 0x0\r
+/* Extracts the ALT_UART_SRR_RFR field value from a register. */\r
+#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)\r
+/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */\r
+#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)\r
+\r
+/*\r
+ * Field : Tx FIFO Reset - xfr\r
+ * \r
+ * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used\r
+ * to remove the burden on software having to store previously written FCR values\r
+ * (which are pretty static) just to reset the transmit FIFO.This resets the\r
+ * control portion of the transmit FIFO and treats the FIFO as empty. This will\r
+ * also de-assert the DMA Tx request and single signals.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------|:------|:-----------------\r
+ * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO\r
+ * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_XFR\r
+ * \r
+ * No reset Tx FIFO\r
+ */\r
+#define ALT_UART_SRR_XFR_E_NORST 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRR_XFR\r
+ * \r
+ * Reset Tx FIFO\r
+ */\r
+#define ALT_UART_SRR_XFR_E_RST 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */\r
+#define ALT_UART_SRR_XFR_LSB 2\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */\r
+#define ALT_UART_SRR_XFR_MSB 2\r
+/* The width in bits of the ALT_UART_SRR_XFR register field. */\r
+#define ALT_UART_SRR_XFR_WIDTH 1\r
+/* The mask used to set the ALT_UART_SRR_XFR register field value. */\r
+#define ALT_UART_SRR_XFR_SET_MSK 0x00000004\r
+/* The mask used to clear the ALT_UART_SRR_XFR register field value. */\r
+#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb\r
+/* The reset value of the ALT_UART_SRR_XFR register field. */\r
+#define ALT_UART_SRR_XFR_RESET 0x0\r
+/* Extracts the ALT_UART_SRR_XFR field value from a register. */\r
+#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)\r
+/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */\r
+#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SRR.\r
+ */\r
+struct ALT_UART_SRR_s\r
+{\r
+ uint32_t ur : 1; /* UART Reset */\r
+ uint32_t rfr : 1; /* Rx FIFO Reset */\r
+ uint32_t xfr : 1; /* Tx FIFO Reset */\r
+ uint32_t : 29; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SRR. */\r
+typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */\r
+#define ALT_UART_SRR_OFST 0x88\r
+/* The address of the ALT_UART_SRR register. */\r
+#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST))\r
+\r
+/*\r
+ * Register : Shadow Request to Send - srts\r
+ * \r
+ * This is a shadow register for the RTS status (MCR[1]), this can be used to\r
+ * remove the burden of having to performing a read modify write on the MCR.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-----------------------\r
+ * [0] | RW | 0x0 | Shadow Request to Send\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Request to Send - srts\r
+ * \r
+ * This is used to directly control the Request to Send (uart_rts_n) output. The\r
+ * Request to Send (uart_rts_n) output is used to inform the modem or data set that\r
+ * the UART is read to exchange data. The uart_rts_n signal is set low by\r
+ * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one)\r
+ * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled\r
+ * in the same way, but is also gated with the receiver FIFO threshold trigger\r
+ * (uart_rts_n is inactive high when above the threshold).\r
+ * \r
+ * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held\r
+ * inactive high while the value of this location is internally looped back to an\r
+ * input.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:------------------\r
+ * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0\r
+ * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRTS_SRTS\r
+ * \r
+ * uart_rts_n logic0\r
+ */\r
+#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRTS_SRTS\r
+ * \r
+ * uart_rts_n logic1\r
+ */\r
+#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */\r
+#define ALT_UART_SRTS_SRTS_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */\r
+#define ALT_UART_SRTS_SRTS_MSB 0\r
+/* The width in bits of the ALT_UART_SRTS_SRTS register field. */\r
+#define ALT_UART_SRTS_SRTS_WIDTH 1\r
+/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */\r
+#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */\r
+#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_SRTS_SRTS register field. */\r
+#define ALT_UART_SRTS_SRTS_RESET 0x0\r
+/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */\r
+#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */\r
+#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SRTS.\r
+ */\r
+struct ALT_UART_SRTS_s\r
+{\r
+ uint32_t srts : 1; /* Shadow Request to Send */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SRTS. */\r
+typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */\r
+#define ALT_UART_SRTS_OFST 0x8c\r
+/* The address of the ALT_UART_SRTS register. */\r
+#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST))\r
+\r
+/*\r
+ * Register : Shadow Break Control Register - sbcr\r
+ * \r
+ * This is a shadow register for the Break bit [6] of the register LCR. This can be\r
+ * used to remove the burden of having to performing a read modify write on the\r
+ * LCR.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:---------------------\r
+ * [0] | RW | 0x0 | Shadow Break Control\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Break Control - sbcr\r
+ * \r
+ * This is used to cause a break condition to be transmitted to the receiving\r
+ * device. If set to one the serial output is forced to the spacing (logic 0)\r
+ * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is\r
+ * forced low until the Break bit is cleared. When in Loopback Mode, the break\r
+ * condition is internally looped back to the receiver.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:----------------------------\r
+ * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break \r
+ * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SBCR_SBCR\r
+ * \r
+ * no break\r
+ */\r
+#define ALT_UART_SBCR_SBCR_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SBCR_SBCR\r
+ * \r
+ * break serial output spacing\r
+ */\r
+#define ALT_UART_SBCR_SBCR_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */\r
+#define ALT_UART_SBCR_SBCR_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */\r
+#define ALT_UART_SBCR_SBCR_MSB 0\r
+/* The width in bits of the ALT_UART_SBCR_SBCR register field. */\r
+#define ALT_UART_SBCR_SBCR_WIDTH 1\r
+/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */\r
+#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */\r
+#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_SBCR_SBCR register field. */\r
+#define ALT_UART_SBCR_SBCR_RESET 0x0\r
+/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */\r
+#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */\r
+#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SBCR.\r
+ */\r
+struct ALT_UART_SBCR_s\r
+{\r
+ uint32_t sbcr : 1; /* Shadow Break Control */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SBCR. */\r
+typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */\r
+#define ALT_UART_SBCR_OFST 0x90\r
+/* The address of the ALT_UART_SBCR register. */\r
+#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST))\r
+\r
+/*\r
+ * Register : Shadow DMA Mode - sdmam\r
+ * \r
+ * This is a shadow register for the DMA mode bit (FCR[3]).\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:----------------\r
+ * [0] | RW | 0x0 | Shadow DMA Mode\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow DMA Mode - sdmam\r
+ * \r
+ * This can be used to remove the burden of having to store the previously written\r
+ * value to the FCR in memory and having to mask this value so that only the DMA\r
+ * Mode bit gets updated.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------------|:------|:---------------------------\r
+ * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode \r
+ * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SDMAM_SDMAM\r
+ * \r
+ * Single DMA Transfer Mode\r
+ */\r
+#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SDMAM_SDMAM\r
+ * \r
+ * Multiple DMA Transfer Mode\r
+ */\r
+#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */\r
+#define ALT_UART_SDMAM_SDMAM_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */\r
+#define ALT_UART_SDMAM_SDMAM_MSB 0\r
+/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */\r
+#define ALT_UART_SDMAM_SDMAM_WIDTH 1\r
+/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */\r
+#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */\r
+#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */\r
+#define ALT_UART_SDMAM_SDMAM_RESET 0x0\r
+/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */\r
+#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */\r
+#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SDMAM.\r
+ */\r
+struct ALT_UART_SDMAM_s\r
+{\r
+ uint32_t sdmam : 1; /* Shadow DMA Mode */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SDMAM. */\r
+typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */\r
+#define ALT_UART_SDMAM_OFST 0x94\r
+/* The address of the ALT_UART_SDMAM register. */\r
+#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST))\r
+\r
+/*\r
+ * Register : Shadow FIFO Enable - sfe\r
+ * \r
+ * This is a shadow register for the FIFO enable bit [0] of register FCR.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------------\r
+ * [0] | RW | 0x0 | Shadow FIFO Enable\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow FIFO Enable - sfe\r
+ * \r
+ * This can be used to remove the burden of having to store the previously written\r
+ * value to the FCR in memory and having to mask this value so that only the FIFO\r
+ * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx\r
+ * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both\r
+ * the Tx and Rx controller portion of FIFO's will be reset.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------|:------|:--------------\r
+ * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx\r
+ * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SFE_SFE\r
+ * \r
+ * Disable Rx/Tx\r
+ */\r
+#define ALT_UART_SFE_SFE_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SFE_SFE\r
+ * \r
+ * Enable Rx/Tx\r
+ */\r
+#define ALT_UART_SFE_SFE_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */\r
+#define ALT_UART_SFE_SFE_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */\r
+#define ALT_UART_SFE_SFE_MSB 0\r
+/* The width in bits of the ALT_UART_SFE_SFE register field. */\r
+#define ALT_UART_SFE_SFE_WIDTH 1\r
+/* The mask used to set the ALT_UART_SFE_SFE register field value. */\r
+#define ALT_UART_SFE_SFE_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_SFE_SFE register field value. */\r
+#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_SFE_SFE register field. */\r
+#define ALT_UART_SFE_SFE_RESET 0x0\r
+/* Extracts the ALT_UART_SFE_SFE field value from a register. */\r
+#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */\r
+#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SFE.\r
+ */\r
+struct ALT_UART_SFE_s\r
+{\r
+ uint32_t sfe : 1; /* Shadow FIFO Enable */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SFE. */\r
+typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */\r
+#define ALT_UART_SFE_OFST 0x98\r
+/* The address of the ALT_UART_SFE register. */\r
+#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST))\r
+\r
+/*\r
+ * Register : Shadow Rx Trigger - srt\r
+ * \r
+ * This is a shadow register for the Rx trigger bits (FCR[7:6]).\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:------------------------\r
+ * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits\r
+ * [31:2] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Rx Trigger Bits - srt\r
+ * \r
+ * This can be used to remove the burden of having to store the previously written\r
+ * value to the FCR in memory and having to mask this value so that only the Rx\r
+ * trigger bit gets updated. This is used to select the trigger level in the\r
+ * receiver FIFO at which the Received Data Available Interrupt will be generated.\r
+ * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA\r
+ * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are\r
+ * supported.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------------|:------|:----------------------\r
+ * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo\r
+ * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full \r
+ * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full \r
+ * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRT_SRT\r
+ * \r
+ * one character in fifo\r
+ */\r
+#define ALT_UART_SRT_SRT_E_ONECHAR 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRT_SRT\r
+ * \r
+ * FIFO 1/4 full\r
+ */\r
+#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRT_SRT\r
+ * \r
+ * FIFO 1/2 full\r
+ */\r
+#define ALT_UART_SRT_SRT_E_HALFFULL 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_SRT_SRT\r
+ * \r
+ * FIFO 2 less than full\r
+ */\r
+#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */\r
+#define ALT_UART_SRT_SRT_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */\r
+#define ALT_UART_SRT_SRT_MSB 1\r
+/* The width in bits of the ALT_UART_SRT_SRT register field. */\r
+#define ALT_UART_SRT_SRT_WIDTH 2\r
+/* The mask used to set the ALT_UART_SRT_SRT register field value. */\r
+#define ALT_UART_SRT_SRT_SET_MSK 0x00000003\r
+/* The mask used to clear the ALT_UART_SRT_SRT register field value. */\r
+#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc\r
+/* The reset value of the ALT_UART_SRT_SRT register field. */\r
+#define ALT_UART_SRT_SRT_RESET 0x0\r
+/* Extracts the ALT_UART_SRT_SRT field value from a register. */\r
+#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */\r
+#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_SRT.\r
+ */\r
+struct ALT_UART_SRT_s\r
+{\r
+ uint32_t srt : 2; /* Shadow Rx Trigger Bits */\r
+ uint32_t : 30; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_SRT. */\r
+typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */\r
+#define ALT_UART_SRT_OFST 0x9c\r
+/* The address of the ALT_UART_SRT register. */\r
+#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST))\r
+\r
+/*\r
+ * Register : Shadow Tx Empty Trigger - stet\r
+ * \r
+ * This is a shadow register for the Tx empty trigger bits (FCR[5:4]).\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-----------------------------\r
+ * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits\r
+ * [31:2] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Shadow Tx Empty Trigger Bits - stet\r
+ * \r
+ * This can be used to remove the burden of having to store the previously written\r
+ * value to the FCR in memory and having to mask this value so that only the Tx\r
+ * empty trigger bit gets updated. This is used to select the empty threshold level\r
+ * at which the THRE Interrupts will be generated when the mode is active. These\r
+ * threshold levels are also described in. The enum trigger levels are supported.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :---------------------------------|:------|:-----------------------\r
+ * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty \r
+ * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO\r
+ * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full \r
+ * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_STET_STET\r
+ * \r
+ * FIFO empty\r
+ */\r
+#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_STET_STET\r
+ * \r
+ * Two characters in FIFO\r
+ */\r
+#define ALT_UART_STET_STET_E_TWOCHARS 0x1\r
+/*\r
+ * Enumerated value for register field ALT_UART_STET_STET\r
+ * \r
+ * FIFO quarter full\r
+ */\r
+#define ALT_UART_STET_STET_E_QUARTERFULL 0x2\r
+/*\r
+ * Enumerated value for register field ALT_UART_STET_STET\r
+ * \r
+ * FIFO half full\r
+ */\r
+#define ALT_UART_STET_STET_E_HALFFULL 0x3\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */\r
+#define ALT_UART_STET_STET_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */\r
+#define ALT_UART_STET_STET_MSB 1\r
+/* The width in bits of the ALT_UART_STET_STET register field. */\r
+#define ALT_UART_STET_STET_WIDTH 2\r
+/* The mask used to set the ALT_UART_STET_STET register field value. */\r
+#define ALT_UART_STET_STET_SET_MSK 0x00000003\r
+/* The mask used to clear the ALT_UART_STET_STET register field value. */\r
+#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc\r
+/* The reset value of the ALT_UART_STET_STET register field. */\r
+#define ALT_UART_STET_STET_RESET 0x0\r
+/* Extracts the ALT_UART_STET_STET field value from a register. */\r
+#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */\r
+#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_STET.\r
+ */\r
+struct ALT_UART_STET_s\r
+{\r
+ uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */\r
+ uint32_t : 30; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_STET. */\r
+typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_STET register from the beginning of the component. */\r
+#define ALT_UART_STET_OFST 0xa0\r
+/* The address of the ALT_UART_STET register. */\r
+#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST))\r
+\r
+/*\r
+ * Register : Halt Tx - htx\r
+ * \r
+ * Used to halt transmission for testing.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:-------------\r
+ * [0] | RW | 0x0 | Halt Tx Bits\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : Halt Tx Bits - htx\r
+ * \r
+ * This register is use to halt transmissions for testing, so that the transmit\r
+ * FIFO can be filled by the master when FIFO's are enabled.\r
+ * \r
+ * Note, if FIFO's are not enabled, the setting of the halt Tx register will have\r
+ * no effect on operation.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :------------------------|:------|:-----------------\r
+ * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled\r
+ * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_HTX_HTX\r
+ * \r
+ * Halt Tx disabled\r
+ */\r
+#define ALT_UART_HTX_HTX_E_DISD 0x0\r
+/*\r
+ * Enumerated value for register field ALT_UART_HTX_HTX\r
+ * \r
+ * Halt Tx enabled\r
+ */\r
+#define ALT_UART_HTX_HTX_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */\r
+#define ALT_UART_HTX_HTX_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */\r
+#define ALT_UART_HTX_HTX_MSB 0\r
+/* The width in bits of the ALT_UART_HTX_HTX register field. */\r
+#define ALT_UART_HTX_HTX_WIDTH 1\r
+/* The mask used to set the ALT_UART_HTX_HTX register field value. */\r
+#define ALT_UART_HTX_HTX_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_HTX_HTX register field value. */\r
+#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_HTX_HTX register field. */\r
+#define ALT_UART_HTX_HTX_RESET 0x0\r
+/* Extracts the ALT_UART_HTX_HTX field value from a register. */\r
+#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */\r
+#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_HTX.\r
+ */\r
+struct ALT_UART_HTX_s\r
+{\r
+ uint32_t htx : 1; /* Halt Tx Bits */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_HTX. */\r
+typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */\r
+#define ALT_UART_HTX_OFST 0xa4\r
+/* The address of the ALT_UART_HTX register. */\r
+#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST))\r
+\r
+/*\r
+ * Register : DMA Software Acknowledge - dmasa\r
+ * \r
+ * DMA Operation Control\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:------|:------------------------------\r
+ * [0] | W | 0x0 | DMA Software Acknowledge Bits\r
+ * [31:1] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : DMA Software Acknowledge Bits - dmasa\r
+ * \r
+ * This register is used to perform DMA software acknowledge if a transfer needs to\r
+ * be terminated due to an error condition. For example, if the DMA disables the\r
+ * channel, then the uart should clear its request. This will cause the Tx request,\r
+ * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is\r
+ * 'self-clearing' and it is not necessary to clear this bit.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */\r
+#define ALT_UART_DMASA_DMASA_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */\r
+#define ALT_UART_DMASA_DMASA_MSB 0\r
+/* The width in bits of the ALT_UART_DMASA_DMASA register field. */\r
+#define ALT_UART_DMASA_DMASA_WIDTH 1\r
+/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */\r
+#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001\r
+/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */\r
+#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe\r
+/* The reset value of the ALT_UART_DMASA_DMASA register field. */\r
+#define ALT_UART_DMASA_DMASA_RESET 0x0\r
+/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */\r
+#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)\r
+/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */\r
+#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_DMASA.\r
+ */\r
+struct ALT_UART_DMASA_s\r
+{\r
+ uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */\r
+ uint32_t : 31; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_DMASA. */\r
+typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */\r
+#define ALT_UART_DMASA_OFST 0xa8\r
+/* The address of the ALT_UART_DMASA register. */\r
+#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST))\r
+\r
+/*\r
+ * Register : Component Parameter Register - cpr\r
+ * \r
+ * Describes various fixed hardware setups states.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :--------|:-------|:------|:----------------------------------\r
+ * [1:0] | R | 0x2 | APB DATA WIDTH \r
+ * [3:2] | ??? | 0x0 | *UNDEFINED* \r
+ * [4] | R | 0x1 | Auto Flow Control \r
+ * [5] | R | 0x1 | THRE MODE \r
+ * [6] | R | 0x0 | SIR MODE Unsupported \r
+ * [7] | R | 0x0 | SIR LP MODE Unsupported \r
+ * [8] | R | 0x1 | ADDITIONAL FEATURES Supported \r
+ * [9] | R | 0x1 | FIFO ACCESS Supported \r
+ * [10] | R | 0x1 | FIFO STAT Supported \r
+ * [11] | R | 0x1 | SHADOW Supported \r
+ * [12] | R | 0x1 | Configuartion ID Register Present\r
+ * [13] | R | 0x1 | DMA EXTRA Supported \r
+ * [15:14] | ??? | 0x0 | *UNDEFINED* \r
+ * [23:16] | R | 0x37 | FIFO Depth \r
+ * [31:24] | ??? | 0x0 | *UNDEFINED* \r
+ * \r
+ */\r
+/*\r
+ * Field : APB DATA WIDTH - apbdatawidth\r
+ * \r
+ * Fixed to support an ABP data bus width of 32-bits.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------------------|:------|:-------------------------\r
+ * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH\r
+ * \r
+ * APB Data Width = 32-bits\r
+ */\r
+#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_MSB 1\r
+/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2\r
+/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003\r
+/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc\r
+/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2\r
+/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0)\r
+/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003)\r
+\r
+/*\r
+ * Field : Auto Flow Control - afce_mode\r
+ * \r
+ * Allows auto flow control.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description\r
+ * :----------------------------|:------|:------------\r
+ * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_AFCE_MOD\r
+ * \r
+ * Auto Flow\r
+ */\r
+#define ALT_UART_CPR_AFCE_MOD_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */\r
+#define ALT_UART_CPR_AFCE_MOD_LSB 4\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */\r
+#define ALT_UART_CPR_AFCE_MOD_MSB 4\r
+/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */\r
+#define ALT_UART_CPR_AFCE_MOD_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */\r
+#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010\r
+/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */\r
+#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef\r
+/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */\r
+#define ALT_UART_CPR_AFCE_MOD_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */\r
+#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4)\r
+/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010)\r
+\r
+/*\r
+ * Field : THRE MODE - thre_mode\r
+ * \r
+ * Programmable Transmitter Hold Register Empty interrupt\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:------------------------------------------\r
+ * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt\r
+ * : | | present \r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_THRE_MOD\r
+ * \r
+ * Programmable Tx Hold Reg. Empty interrupt present\r
+ */\r
+#define ALT_UART_CPR_THRE_MOD_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */\r
+#define ALT_UART_CPR_THRE_MOD_LSB 5\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */\r
+#define ALT_UART_CPR_THRE_MOD_MSB 5\r
+/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */\r
+#define ALT_UART_CPR_THRE_MOD_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */\r
+#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020\r
+/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */\r
+#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf\r
+/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */\r
+#define ALT_UART_CPR_THRE_MOD_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */\r
+#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5)\r
+/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020)\r
+\r
+/*\r
+ * Field : SIR MODE Unsupported - sir_mode\r
+ * \r
+ * Sir mode not used in this application.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :----------------------------|:------|:-----------------------\r
+ * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_SIR_MOD\r
+ * \r
+ * Sir Mode Not Supported\r
+ */\r
+#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */\r
+#define ALT_UART_CPR_SIR_MOD_LSB 6\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */\r
+#define ALT_UART_CPR_SIR_MOD_MSB 6\r
+/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */\r
+#define ALT_UART_CPR_SIR_MOD_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */\r
+#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040\r
+/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */\r
+#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf\r
+/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */\r
+#define ALT_UART_CPR_SIR_MOD_RESET 0x0\r
+/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */\r
+#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6)\r
+/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040)\r
+\r
+/*\r
+ * Field : SIR LP MODE Unsupported - sir_lp_mode\r
+ * \r
+ * LP Sir Mode not used in this application.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------------|:------|:--------------------------\r
+ * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD\r
+ * \r
+ * LP Sir Mode Not Supported\r
+ */\r
+#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_LSB 7\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_MSB 7\r
+/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080\r
+/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f\r
+/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0\r
+/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7)\r
+/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080)\r
+\r
+/*\r
+ * Field : ADDITIONAL FEATURES Supported - additional_feat\r
+ * \r
+ * Configures the uart to include fifo status register, shadow registers and\r
+ * encoded parameter register.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------------|:------|:------------------------------\r
+ * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT\r
+ * \r
+ * Additional Features Supported\r
+ */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8\r
+/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100\r
+/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff\r
+/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)\r
+/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)\r
+\r
+/*\r
+ * Field : FIFO ACCESS Supported - fifo_access\r
+ * \r
+ * Configures the peripheral to have a programmable FIFO access mode. This is used\r
+ * for test purposes, to allow the receiver FIFO to be written and the transmit\r
+ * FIFO to be read when FIFOs are implemented and enabled.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------------|:------|:----------------------\r
+ * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS\r
+ * \r
+ * FIFO Access Supported\r
+ */\r
+#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_LSB 9\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_MSB 9\r
+/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200\r
+/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff\r
+/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)\r
+/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)\r
+\r
+/*\r
+ * Field : FIFO STAT Supported - fifo_stat\r
+ * \r
+ * Configures the peripheral to have three additional FIFO status registers.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------|:------|:--------------------\r
+ * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_FIFO_STAT\r
+ * \r
+ * FIFO Stat Supported\r
+ */\r
+#define ALT_UART_CPR_FIFO_STAT_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */\r
+#define ALT_UART_CPR_FIFO_STAT_LSB 10\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */\r
+#define ALT_UART_CPR_FIFO_STAT_MSB 10\r
+/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */\r
+#define ALT_UART_CPR_FIFO_STAT_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */\r
+#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400\r
+/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */\r
+#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff\r
+/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */\r
+#define ALT_UART_CPR_FIFO_STAT_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */\r
+#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)\r
+/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)\r
+\r
+/*\r
+ * Field : SHADOW Supported - shadow\r
+ * \r
+ * Configures the peripheral to have seven additional registers that shadow some of\r
+ * the existing register bits that are regularly modified by software. These can be\r
+ * used to reduce the software overhead that is introduced by having to perform\r
+ * read-modify writes.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------|:------|:-----------------\r
+ * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_SHADOW\r
+ * \r
+ * Shadow Supported\r
+ */\r
+#define ALT_UART_CPR_SHADOW_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */\r
+#define ALT_UART_CPR_SHADOW_LSB 11\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */\r
+#define ALT_UART_CPR_SHADOW_MSB 11\r
+/* The width in bits of the ALT_UART_CPR_SHADOW register field. */\r
+#define ALT_UART_CPR_SHADOW_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */\r
+#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800\r
+/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */\r
+#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff\r
+/* The reset value of the ALT_UART_CPR_SHADOW register field. */\r
+#define ALT_UART_CPR_SHADOW_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */\r
+#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)\r
+/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)\r
+\r
+/*\r
+ * Field : Configuartion ID Register Present - uart_add_encoded_param\r
+ * \r
+ * Configures the peripheral to have a configuration identification register.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :--------------------------------------|:------|:--------------------\r
+ * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM\r
+ * \r
+ * ID register present\r
+ */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12\r
+/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000\r
+/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff\r
+/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12)\r
+/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000)\r
+\r
+/*\r
+ * Field : DMA EXTRA Supported - dma_extra\r
+ * \r
+ * Configures the peripheral to have four additional DMA signals on the interface.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-----------------------------|:------|:--------------------\r
+ * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA\r
+ * \r
+ * DMA Extra Supported\r
+ */\r
+#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */\r
+#define ALT_UART_CPR_DMA_EXTRA_LSB 13\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */\r
+#define ALT_UART_CPR_DMA_EXTRA_MSB 13\r
+/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */\r
+#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1\r
+/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */\r
+#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000\r
+/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */\r
+#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff\r
+/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */\r
+#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1\r
+/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */\r
+#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)\r
+/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)\r
+\r
+/*\r
+ * Field : FIFO Depth - fifo_mode\r
+ * \r
+ * Receiver and Transmitter FIFO depth in bytes.\r
+ * \r
+ * Field Enumeration Values:\r
+ * \r
+ * Enum | Value | Description \r
+ * :-------------------------------------|:------|:---------------------\r
+ * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/*\r
+ * Enumerated value for register field ALT_UART_CPR_FIFO_MOD\r
+ * \r
+ * FIFO Depth 128 bytes\r
+ */\r
+#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80\r
+\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */\r
+#define ALT_UART_CPR_FIFO_MOD_LSB 16\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */\r
+#define ALT_UART_CPR_FIFO_MOD_MSB 23\r
+/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */\r
+#define ALT_UART_CPR_FIFO_MOD_WIDTH 8\r
+/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */\r
+#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000\r
+/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */\r
+#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff\r
+/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */\r
+#define ALT_UART_CPR_FIFO_MOD_RESET 0x37\r
+/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */\r
+#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16)\r
+/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */\r
+#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_CPR.\r
+ */\r
+struct ALT_UART_CPR_s\r
+{\r
+ const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */\r
+ uint32_t : 2; /* *UNDEFINED* */\r
+ const uint32_t afce_mode : 1; /* Auto Flow Control */\r
+ const uint32_t thre_mode : 1; /* THRE MODE */\r
+ const uint32_t sir_mode : 1; /* SIR MODE Unsupported */\r
+ const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */\r
+ const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */\r
+ const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */\r
+ const uint32_t fifo_stat : 1; /* FIFO STAT Supported */\r
+ const uint32_t shadow : 1; /* SHADOW Supported */\r
+ const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */\r
+ const uint32_t dma_extra : 1; /* DMA EXTRA Supported */\r
+ uint32_t : 2; /* *UNDEFINED* */\r
+ const uint32_t fifo_mode : 8; /* FIFO Depth */\r
+ uint32_t : 8; /* *UNDEFINED* */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_CPR. */\r
+typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */\r
+#define ALT_UART_CPR_OFST 0xf4\r
+/* The address of the ALT_UART_CPR register. */\r
+#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))\r
+\r
+/*\r
+ * Register : Component Version - ucv\r
+ * \r
+ * Used only with Additional Features\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:-----------|:--------------\r
+ * [31:0] | R | 0x3331312a | ASCII version\r
+ * \r
+ */\r
+/*\r
+ * Field : ASCII version - uart_component_version\r
+ * \r
+ * ASCII value for each number in the version, followed by *For example 32_30_31_2A\r
+ * represents the version 2.01a\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31\r
+/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32\r
+/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff\r
+/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000\r
+/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a\r
+/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */\r
+#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_UCV.\r
+ */\r
+struct ALT_UART_UCV_s\r
+{\r
+ const uint32_t uart_component_version : 32; /* ASCII version */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_UCV. */\r
+typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */\r
+#define ALT_UART_UCV_OFST 0xf8\r
+/* The address of the ALT_UART_UCV register. */\r
+#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST))\r
+\r
+/*\r
+ * Register : Component Type Register - ctr\r
+ * \r
+ * Describes a hex value associated with the component.\r
+ * \r
+ * Register Layout\r
+ * \r
+ * Bits | Access | Reset | Description \r
+ * :-------|:-------|:-----------|:--------------\r
+ * [31:0] | R | 0x44570110 | Peripheral ID\r
+ * \r
+ */\r
+/*\r
+ * Field : Peripheral ID - peripheral_id\r
+ * \r
+ * This register contains the peripherals identification code.\r
+ * \r
+ * Field Access Macros:\r
+ * \r
+ */\r
+/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0\r
+/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31\r
+/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32\r
+/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff\r
+/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000\r
+/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110\r
+/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)\r
+/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */\r
+#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register ALT_UART_CTR.\r
+ */\r
+struct ALT_UART_CTR_s\r
+{\r
+ const uint32_t peripheral_id : 32; /* Peripheral ID */\r
+};\r
+\r
+/* The typedef declaration for register ALT_UART_CTR. */\r
+typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */\r
+#define ALT_UART_CTR_OFST 0xfc\r
+/* The address of the ALT_UART_CTR register. */\r
+#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST))\r
+\r
+#ifndef __ASSEMBLY__\r
+/*\r
+ * WARNING: The C register and register group struct declarations are provided for\r
+ * convenience and illustrative purposes. They should, however, be used with\r
+ * caution as the C language standard provides no guarantees about the alignment or\r
+ * atomicity of device memory accesses. The recommended practice for writing\r
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
+ * alt_write_word() functions.\r
+ * \r
+ * The struct declaration for register group ALT_UART.\r
+ */\r
+struct ALT_UART_s\r
+{\r
+ volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */\r
+ volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */\r
+ /* Union for registers colocated at base address offset #0x. */\r
+ union\r
+ {\r
+ volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */\r
+ volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */\r
+ } _u_0x8;\r
+ volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */\r
+ volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */\r
+ volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */\r
+ volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */\r
+ volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */\r
+ volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */\r
+ volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */\r
+ volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */\r
+ volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */\r
+ volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */\r
+ volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */\r
+ volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */\r
+ volatile ALT_UART_USR_t usr; /* ALT_UART_USR */\r
+ volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */\r
+ volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */\r
+ volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */\r
+ volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */\r
+ volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */\r
+ volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */\r
+ volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */\r
+ volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */\r
+ volatile ALT_UART_STET_t stet; /* ALT_UART_STET */\r
+ volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */\r
+ volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */\r
+ volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */\r
+ volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */\r
+ volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */\r
+ volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */\r
+};\r
+\r
+/* The typedef declaration for register group ALT_UART. */\r
+typedef volatile struct ALT_UART_s ALT_UART_t;\r
+/* The struct declaration for the raw register contents of register group ALT_UART. */\r
+struct ALT_UART_raw_s\r
+{\r
+ volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */\r
+ volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */\r
+ /* Union for registers colocated at base address offset #0x. */\r
+ union\r
+ {\r
+ volatile uint32_t iir; /* ALT_UART_IIR */\r
+ volatile uint32_t fcr; /* ALT_UART_FCR */\r
+ } _u_0x8;\r
+ volatile uint32_t lcr; /* ALT_UART_LCR */\r
+ volatile uint32_t mcr; /* ALT_UART_MCR */\r
+ volatile uint32_t lsr; /* ALT_UART_LSR */\r
+ volatile uint32_t msr; /* ALT_UART_MSR */\r
+ volatile uint32_t scr; /* ALT_UART_SCR */\r
+ volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */\r
+ volatile uint32_t srbr; /* ALT_UART_SRBR */\r
+ volatile uint32_t sthr; /* ALT_UART_STHR */\r
+ volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */\r
+ volatile uint32_t far; /* ALT_UART_FAR */\r
+ volatile uint32_t tfr; /* ALT_UART_TFR */\r
+ volatile uint32_t RFW; /* ALT_UART_RFW */\r
+ volatile uint32_t usr; /* ALT_UART_USR */\r
+ volatile uint32_t tfl; /* ALT_UART_TFL */\r
+ volatile uint32_t rfl; /* ALT_UART_RFL */\r
+ volatile uint32_t srr; /* ALT_UART_SRR */\r
+ volatile uint32_t srts; /* ALT_UART_SRTS */\r
+ volatile uint32_t sbcr; /* ALT_UART_SBCR */\r
+ volatile uint32_t sdmam; /* ALT_UART_SDMAM */\r
+ volatile uint32_t sfe; /* ALT_UART_SFE */\r
+ volatile uint32_t srt; /* ALT_UART_SRT */\r
+ volatile uint32_t stet; /* ALT_UART_STET */\r
+ volatile uint32_t htx; /* ALT_UART_HTX */\r
+ volatile uint32_t dmasa; /* ALT_UART_DMASA */\r
+ volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */\r
+ volatile uint32_t cpr; /* ALT_UART_CPR */\r
+ volatile uint32_t ucv; /* ALT_UART_UCV */\r
+ volatile uint32_t ctr; /* ALT_UART_CTR */\r
+};\r
+\r
+/* The typedef declaration for the raw register contents of register group ALT_UART. */\r
+typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+#endif /* __ALTERA_ALT_UART_H__ */\r
+\r
projects / freertos / blobdiff