RZ RVDS and IAR projects.

[freertos] / FreeRTOS / Demo / CORTEX_A9_RZ_R7S72100_IAR_DS-5 / Source / RenesasFiles / common / vbar_init.s

diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/common/vbar_init.s
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+;/*******************************************************************************\r
+;* DISCLAIMER\r
+;* This software is supplied by Renesas Electronics Corporation and is only\r
+;* intended for use with Renesas products. No other uses are authorized. This\r
+;* software is owned by Renesas Electronics Corporation and is protected under\r
+;* all applicable laws, including copyright laws.\r
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+;* Renesas reserves the right, without notice, to make changes to this software\r
+;* and to discontinue the availability of this software. By using this software,\r
+;* you agree to the additional terms and conditions found by accessing the\r
+;* following link:\r
+;* http://www.renesas.com/disclaimer\r
+;*\r
+;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* File Name     : vbar_init.s\r
+;* Version       : 0.01\r
+;* Device(s)     : Aragon\r
+;* Tool-Chain    : DS-5 Ver 5.8\r
+;*                 ARM Complier \r
+;*               : \r
+;* H/W Platform  : Aragon CPU Board\r
+;* Description   : Aragon Sample Program\r
+;*******************************************************************************/\r
+;/*******************************************************************************\r
+;* History : DD.MM.YYYY Version Description\r
+;*         : 23.05.2012 0.01\r
+;*******************************************************************************/\r
+\r
+;==================================================================\r
+; This code provides basic global enable for Cortex-A9 cache.\r
+; It also enables branch prediction\r
+; This code must be run from a privileged mode\r
+;==================================================================\r
+       AREA   INIT_VBAR, CODE, READONLY\r
+       \r
+       IMPORT  ||Image$$VECTOR_MIRROR_TABLE$$Base||\r
+;      IMPORT  ||Image$$VECTOR_TABLE$$Base||\r
+       \r
+       EXPORT  VbarInit\r
+\r
+VbarInit       FUNCTION\r
+\r
+;===================================================================\r
+; Set Vector Base Address Register (VBAR) to point to this application's vector table\r
+;===================================================================\r
+       LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base||\r
+;      LDR r0, =||Image$$VECTOR_TABLE$$Base||\r
+       MCR p15, 0, r0, c12, c0, 0\r
+\r
+       BX              lr\r
+\r
+       ENDFUNC\r
+\r
+\r
+\r
+\r
+       END\r