Demo application related:

[freertos] / FreeRTOS / Demo / CORTEX_A9_RZ_R7S72100_IAR_DS-5 / target_scripts / init_RZ-A1H.ds

diff --git a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
index 0f142a81338d42ac24771ce8112c4adeaf6bf779..3300f21d64499551271cc7f54292e3ea53b49aff 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
+++ b/FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/target_scripts/init_RZ-A1H.ds
@@ -1,11 +1,10 @@
-stop\r
-pause 500\r
 reset\r
 stop\r
 #reset\r
 \r
 info memory\r
 memory S:0x00000000 S:0x07ffffff ro\r
+memory S:0x08000000 S:0x0fffffff cache\r
 memory S:0x3fffff80 S:0x3fffffff nocache noverify\r
 memory S:0xfcfe0000 S:0xfcfeffff nocache noverify\r
 \r
@@ -21,7 +20,8 @@ mem set 0x3fffff80 32 0x00000001
 \r
 # ;*Writing to On-Chip Data-Retention RAM is enabled.\r
 # ;SYSCR3.RRAMWE3=RRAMWE2=RRAMWE1=RRAMWE0=1\r
-mem set 0xfcfe0408 32 0xf\r
+memory set S:0xFCFE0408 0 {(unsigned char)0x0F}\r
+x/1b 0xfcfe0408\r
 \r
 ######################################\r
 # CS0 Port Setting                                     ##\r
@@ -39,12 +39,6 @@ mem set 0xfcfe3A20 16 0x0000        # PFCAE8
 mem set 0xfcfe3620 16 0x0000        # PFCE8\r
 mem set 0xfcfe3520 16 0x0000        # PFC8\r
 mem set 0xfcfe7220 16 0xffff        # PIPC8\r
-# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),\r
-mem set 0xfcfe341c 16 0xff41        # PMC7\r
-mem set 0xfcfe3A1c 16 0x0000        # PFCAE7\r
-mem set 0xfcfe361c 16 0x0000        # PFCE7\r
-mem set 0xfcfe351c 16 0x0000        # PFC7\r
-mem set 0xfcfe721c 16 0xff41        # PIPC7\r
 # P3_7(CS1#),\r
 mem set 0xfcfe340c 16 0x0080        # PMC3\r
 mem set 0xfcfe3A0c 16 0x0080        # PFCAE3\r
@@ -52,3 +46,47 @@ mem set 0xfcfe360c 16 0x0080        # PFCE3
 mem set 0xfcfe350c 16 0x0000        # PFC3\r
 mem set 0xfcfe720c 16 0x0080        # PIPC3\r
 \r
+# SRSR - SDRAM Setup?\r
+# P7_8(RD#), P7_7(WE1#), P7_6(WE0#), P7_5(RD/WR#), P7_4(CKE), P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#)\r
+mem set 0xfcfe341c 16 0xffff        # PMC7\r
+mem set 0xfcfe3A1c 16 0x0000        # PFCAE7\r
+mem set 0xfcfe361c 16 0x0000        # PFCE7\r
+mem set 0xfcfe351c 16 0x0000        # PFC7\r
+mem set 0xfcfe721c 16 0xffff        # PIPC7\r
+# P5_8(CS2#),\r
+mem set 0xfcfe3414 16 0x0100        # PMC5\r
+mem set 0xfcfe3A14 16 0x0100        # PFCAE5\r
+mem set 0xfcfe3614 16 0x0000        # PFCE5\r
+mem set 0xfcfe3514 16 0x0100        # PFC5\r
+mem set 0xfcfe7214 16 0x0100        # PIPC5\r
+\r
+# disable verify on SDRAM setup registers\r
+memory S:0x3fffc000 S:0x3fffffff nocache noverify\r
+\r
+######################################\r
+# CS2 SDRAM Setting                 ##\r
+######################################\r
+mem set 0x3fffc00c 32 0x00004C00    # CS2BCR - SDRAM\r
+mem set 0x3fffc030 32 0x00000080    # CS2WCR - SDRAM\r
+mem set 0x3fffd040 16 0x0000        # SDRAM_MODE_CS2\r
+\r
+######################################\r
+# CS3 SDRAM Setting                 ##\r
+######################################\r
+wait 0.5s\r
+mem set 0x3fffc010 32 0x00004C00    # CS3BCR - SDRAM\r
+mem set 0x3fffc034 32 0x00002492    # CS3WCR - SDRAM\r
+mem set 0x3fffc04c 32 0x00120812    # SDCR\r
+mem set 0x3fffc058 32 0xA55A0020    # RTCOR\r
+mem set 0x3fffc050 32 0xA55A0010    # RTCSR\r
+mem set 0x3fffe040 16 0x0000        # SDRAM_MODE_CS3\r
+# SRSR - SDRAM Setup?\r
+\r
+#SRSR - Not used - updated to include SDRAM setup\r
+# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),\r
+#mem set 0xfcfe341c 16 0xff41        # PMC7\r
+#mem set 0xfcfe3A1c 16 0x0000        # PFCAE7\r
+#mem set 0xfcfe361c 16 0x0000        # PFCE7\r
+#mem set 0xfcfe351c 16 0x0000        # PFC7\r
+#mem set 0xfcfe721c 16 0xff41        # PIPC7\r
+#SRSR - Not used - updated to include SDRAM setup\r