Move the Zynq's lwIP example from the Full demo into its own configuration as having...

[freertos] / FreeRTOS / Demo / CORTEX_A9_Zynq_ZC702 / RTOSDemo / src / Full_Demo / reg_test.S

diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S
index 694113edc5645b45ddd3036f9fb9d7bcf492944b..20c4de57f71acef2238b673e39d7170976cb465e 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S
@@ -1,5 +1,5 @@
 /*\r
-    FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+    FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
 \r
     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
@@ -81,6 +81,7 @@
        .arm\r
 \r
        /* This function is explained in the comments at the top of main-full.c. */\r
+.type vRegTest1Implementation, %function\r
 vRegTest1Implementation:\r
 \r
        /* Fill each general purpose register with a known value. */\r
@@ -370,6 +371,7 @@ reg1_error_loop:
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.type vRegTest2Implementation, %function\r
 vRegTest2Implementation:\r
 \r
        /* Put a known value in each register. */\r