Completely re-generate the Zynq 7000 demo using the 2016.1 SDK tools.

[freertos] / FreeRTOS / Demo / CORTEX_A9_Zynq_ZC702 / RTOSDemo / src / lscript.ld

diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld
new file mode 100644 (file)
index 0000000..933ba3b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld
@@ -0,0 +1,289 @@
+/*******************************************************************/\r
+/*                                                                 */\r
+/* This file is automatically generated by linker script generator.*/\r
+/*                                                                 */\r
+/* Version:                                 */\r
+/*                                                                 */\r
+/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           */\r
+/*                                                                 */\r
+/* Description : Cortex-A9 Linker Script                          */\r
+/*                                                                 */\r
+/*******************************************************************/\r
+\r
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;\r
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;\r
+\r
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;\r
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;\r
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;\r
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;\r
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;\r
+\r
+/* Define Memories in the system */\r
+\r
+MEMORY\r
+{\r
+   ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x3FF00000\r
+   ps7_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xFC000000, LENGTH = 0x1000000\r
+   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x30000\r
+   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00\r
+}\r
+\r
+/* Specify the default entry point to the program */\r
+\r
+ENTRY(_vector_table)\r
+\r
+/* Define the sections, and where they are mapped in memory */\r
+\r
+SECTIONS\r
+{\r
+.text : {\r
+   *(.freertos_vectors)\r
+   *(.vectors)\r
+   *(.boot)\r
+   *(.text)\r
+   *(.text.*)\r
+   *(.gnu.linkonce.t.*)\r
+   *(.plt)\r
+   *(.gnu_warning)\r
+   *(.gcc_execpt_table)\r
+   *(.glue_7)\r
+   *(.glue_7t)\r
+   *(.vfp11_veneer)\r
+   *(.ARM.extab)\r
+   *(.gnu.linkonce.armextab.*)\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.init : {\r
+   KEEP (*(.init))\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.fini : {\r
+   KEEP (*(.fini))\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.rodata : {\r
+   __rodata_start = .;\r
+   *(.rodata)\r
+   *(.rodata.*)\r
+   *(.gnu.linkonce.r.*)\r
+   __rodata_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.rodata1 : {\r
+   __rodata1_start = .;\r
+   *(.rodata1)\r
+   *(.rodata1.*)\r
+   __rodata1_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.sdata2 : {\r
+   __sdata2_start = .;\r
+   *(.sdata2)\r
+   *(.sdata2.*)\r
+   *(.gnu.linkonce.s2.*)\r
+   __sdata2_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.sbss2 : {\r
+   __sbss2_start = .;\r
+   *(.sbss2)\r
+   *(.sbss2.*)\r
+   *(.gnu.linkonce.sb2.*)\r
+   __sbss2_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.data : {\r
+   __data_start = .;\r
+   *(.data)\r
+   *(.data.*)\r
+   *(.gnu.linkonce.d.*)\r
+   *(.jcr)\r
+   *(.got)\r
+   *(.got.plt)\r
+   __data_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.data1 : {\r
+   __data1_start = .;\r
+   *(.data1)\r
+   *(.data1.*)\r
+   __data1_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.got : {\r
+   *(.got)\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.ctors : {\r
+   __CTOR_LIST__ = .;\r
+   ___CTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.ctors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r
+   KEEP (*(SORT(.ctors.*)))\r
+   KEEP (*(.ctors))\r
+   __CTOR_END__ = .;\r
+   ___CTORS_END___ = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.dtors : {\r
+   __DTOR_LIST__ = .;\r
+   ___DTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.dtors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r
+   KEEP (*(SORT(.dtors.*)))\r
+   KEEP (*(.dtors))\r
+   __DTOR_END__ = .;\r
+   ___DTORS_END___ = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.fixup : {\r
+   __fixup_start = .;\r
+   *(.fixup)\r
+   __fixup_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.eh_frame : {\r
+   *(.eh_frame)\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.eh_framehdr : {\r
+   __eh_framehdr_start = .;\r
+   *(.eh_framehdr)\r
+   __eh_framehdr_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.gcc_except_table : {\r
+   *(.gcc_except_table)\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.mmu_tbl (ALIGN(16384)) : {\r
+   __mmu_tbl_start = .;\r
+   *(.mmu_tbl)\r
+   __mmu_tbl_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.ARM.exidx : {\r
+   __exidx_start = .;\r
+   *(.ARM.exidx*)\r
+   *(.gnu.linkonce.armexidix.*.*)\r
+   __exidx_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.preinit_array : {\r
+   __preinit_array_start = .;\r
+   KEEP (*(SORT(.preinit_array.*)))\r
+   KEEP (*(.preinit_array))\r
+   __preinit_array_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.init_array : {\r
+   __init_array_start = .;\r
+   KEEP (*(SORT(.init_array.*)))\r
+   KEEP (*(.init_array))\r
+   __init_array_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.fini_array : {\r
+   __fini_array_start = .;\r
+   KEEP (*(SORT(.fini_array.*)))\r
+   KEEP (*(.fini_array))\r
+   __fini_array_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.ARM.attributes : {\r
+   __ARM.attributes_start = .;\r
+   *(.ARM.attributes)\r
+   __ARM.attributes_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.sdata : {\r
+   __sdata_start = .;\r
+   *(.sdata)\r
+   *(.sdata.*)\r
+   *(.gnu.linkonce.s.*)\r
+   __sdata_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.sbss (NOLOAD) : {\r
+   __sbss_start = .;\r
+   *(.sbss)\r
+   *(.sbss.*)\r
+   *(.gnu.linkonce.sb.*)\r
+   __sbss_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.tdata : {\r
+   __tdata_start = .;\r
+   *(.tdata)\r
+   *(.tdata.*)\r
+   *(.gnu.linkonce.td.*)\r
+   __tdata_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.tbss : {\r
+   __tbss_start = .;\r
+   *(.tbss)\r
+   *(.tbss.*)\r
+   *(.gnu.linkonce.tb.*)\r
+   __tbss_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.bss (NOLOAD) : {\r
+   __bss_start = .;\r
+   *(.bss)\r
+   *(.bss.*)\r
+   *(.gnu.linkonce.b.*)\r
+   *(COMMON)\r
+   __bss_end = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\r
+\r
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );\r
+\r
+/* Generate Stack and Heap definitions */\r
+\r
+.heap (NOLOAD) : {\r
+   . = ALIGN(16);\r
+   _heap = .;\r
+   HeapBase = .;\r
+   _heap_start = .;\r
+   . += _HEAP_SIZE;\r
+   _heap_end = .;\r
+   HeapLimit = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+.stack (NOLOAD) : {\r
+   . = ALIGN(16);\r
+   _stack_end = .;\r
+   . += _STACK_SIZE;\r
+   . = ALIGN(16);\r
+   _stack = .;\r
+   __stack = _stack;\r
+   . = ALIGN(16);\r
+   _irq_stack_end = .;\r
+   . += _IRQ_STACK_SIZE;\r
+   . = ALIGN(16);\r
+   __irq_stack = .;\r
+   _supervisor_stack_end = .;\r
+   . += _SUPERVISOR_STACK_SIZE;\r
+   . = ALIGN(16);\r
+   __supervisor_stack = .;\r
+   _abort_stack_end = .;\r
+   . += _ABORT_STACK_SIZE;\r
+   . = ALIGN(16);\r
+   __abort_stack = .;\r
+   _fiq_stack_end = .;\r
+   . += _FIQ_STACK_SIZE;\r
+   . = ALIGN(16);\r
+   __fiq_stack = .;\r
+   _undef_stack_end = .;\r
+   . += _UNDEF_STACK_SIZE;\r
+   . = ALIGN(16);\r
+   __undef_stack = .;\r
+} > ps7_ddr_0_S_AXI_BASEADDR\r
+\r
+_end = .;\r
+}\r
+\r