Add SAM3X-EK demo.

[freertos] / FreeRTOS / Demo / CORTEX_ATSAM3X_Atmel_Studio / src / asf / sam / utils / cmsis / sam3x / include / instance / instance_usart0.h

diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h
new file mode 100644 (file)
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+++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h
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+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ *    this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ *    this list of conditions and the following disclaimer in the documentation\r
+ *    and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ *    Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART0_INSTANCE_\r
+#define _SAM3XA_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART0_CR          (0x40098000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR          (0x40098004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER          (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR          (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR          (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR          (0x40098014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR          (0x40098018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR          (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR          (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR          (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR          (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI          (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER          (0x40098044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF          (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN          (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_LINMR          (0x40098054U) /**< \brief (USART0) LIN Mode Register */\r
+#define REG_USART0_LINIR          (0x40098058U) /**< \brief (USART0) LIN Identifier Register */\r
+#define REG_USART0_WPMR          (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR          (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR          (0x40098100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR          (0x40098104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR          (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR          (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR          (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR          (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR          (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR          (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR          (0x40098120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR          (0x40098124U) /**< \brief (USART0) Transfer Status Register */\r
+#else\r
+#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */\r
+#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */\r
+#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART0_INSTANCE_ */\r