Add SAM3X-EK demo.

[freertos] / FreeRTOS / Demo / CORTEX_ATSAM3X_Atmel_Studio / src / asf / sam / utils / cmsis / sam3x / include / instance / instance_usart1.h

diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h
new file mode 100644 (file)
index 0000000..e0fa053
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h
@@ -0,0 +1,108 @@
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ *    this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ *    this list of conditions and the following disclaimer in the documentation\r
+ *    and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ *    Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART1_INSTANCE_\r
+#define _SAM3XA_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART1_CR          (0x4009C000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR          (0x4009C004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER          (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR          (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR          (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR          (0x4009C014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR          (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR          (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR          (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR          (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR          (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI          (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER          (0x4009C044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF          (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN          (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_LINMR          (0x4009C054U) /**< \brief (USART1) LIN Mode Register */\r
+#define REG_USART1_LINIR          (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */\r
+#define REG_USART1_WPMR          (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR          (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR          (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR          (0x4009C104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR          (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR          (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR          (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR          (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR          (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR          (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR          (0x4009C120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR          (0x4009C124U) /**< \brief (USART1) Transfer Status Register */\r
+#else\r
+#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */\r
+#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */\r
+#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART1_INSTANCE_ */\r