--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X4E_\r
+#define _SAM3X4E_\r
+\r
+/** \addtogroup SAM3X4E_definitions SAM3X4E definitions\r
+ This file defines all structures and symbols for SAM3X4E:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X4E specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X4E Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X4E Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X4E Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X4E Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X4E Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X4E Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X4E Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X4E Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X4E Universal Asynchronous Receiver Transceiver (UART) */\r
+ SMC_IRQn = 9, /**< 9 SAM3X4E Static Memory Controller (SMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X4E Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X4E Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM3X4E Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 14, /**< 14 SAM3X4E Parallel I/O Controller D (PIOD) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X4E USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X4E USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X4E USART 2 (USART2) */\r
+ USART3_IRQn = 20, /**< 20 SAM3X4E USART 3 (USART3) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X4E Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X4E Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X4E Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X4E Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X4E Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X4E Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X4E Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X4E Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X4E Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X4E Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X4E Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 33, /**< 33 SAM3X4E Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 34, /**< 34 SAM3X4E Timer Counter 7 (TC7) */\r
+ TC8_IRQn = 35, /**< 35 SAM3X4E Timer Counter 8 (TC8) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X4E Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X4E ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X4E DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X4E DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X4E USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X4E True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X4E Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X4E CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X4E CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pfnSMC_Handler; /* 9 Static Memory Controller */\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pfnUSART3_Handler; /* 20 USART 3 */\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 33 Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 34 Timer Counter 7 */\r
+ void* pfnTC8_Handler; /* 35 Timer Counter 8 */\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USART3_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X4E does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X4E uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usart3.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */\r
+#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */\r
+#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x4e.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x20000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (512u)\r
+#define IFLASH1_SIZE (0x20000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (512u)\r
+#define IRAM0_SIZE (0x8000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define NFCRAM_SIZE (0x1000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X4E_ */\r
projects / freertos / blobdiff