--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "system_sam3x.h"\r
+#include "sam3xa.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock settings (84MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0xdUL) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fUL) \\r
+ | CKGR_PLLAR_DIVA(0x1UL))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+/* Clock Definitions */\r
+#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */\r
+\r
+/* FIXME: should be generated by sock */\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
+\r
+ /* Initialize main oscillator */\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
+\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
+ }\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | \r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+ case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> \r
+ CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> \r
+ CKGR_PLLAR_DIVA_Pos));\r
+ } else {\r
+ SystemCoreClock = SYS_UTMIPLL / 2U;\r
+ }\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> \r
+ PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk)\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
projects / freertos / blobdiff