Add Pearl Gecko demo.

[freertos] / FreeRTOS / Demo / CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio / Source / SilLabs_Code / Device / SiliconLabs / EFM32WG / Include / system_efm32wg.h

diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/system_efm32wg.h b/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/system_efm32wg.h
index 7ed5c9c18b42cc786e4c0a25d1fe81f9e70076af..f4b8c086a7d49c2b8d68329681f39af215a21748 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/system_efm32wg.h
+++ b/FreeRTOS/Demo/CORTEX_EFM32_Gecko_Starter_Kit_Simplicity_Studio/Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Include/system_efm32wg.h
@@ -1,10 +1,10 @@
 /***************************************************************************//**\r
  * @file system_efm32wg.h\r
  * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
  ******************************************************************************\r
  * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
  ******************************************************************************\r
  *\r
  * Permission is granted to anyone to use this software for any purpose,\r
@@ -30,8 +30,8 @@
  *\r
  *****************************************************************************/\r
 \r
-#ifndef __SYSTEM_EFM32WG_H\r
-#define __SYSTEM_EFM32WG_H\r
+#ifndef SYSTEM_EFM32WG_H\r
+#define SYSTEM_EFM32WG_H\r
 \r
 #ifdef __cplusplus\r
 extern "C" {\r
@@ -50,7 +50,6 @@ extern uint32_t SystemCoreClock;    /**< System Clock Frequency (Core Clock) */
  ******************************************************************************/\r
 \r
 /* Interrupt routines - prototypes */\r
-#if defined(_EFM32_WONDER_FAMILY)\r
 void Reset_Handler(void);\r
 void NMI_Handler(void);\r
 void HardFault_Handler(void);\r
@@ -61,6 +60,7 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);\r
 void PendSV_Handler(void);\r
 void SysTick_Handler(void);\r
+\r
 void DMA_IRQHandler(void);\r
 void GPIO_EVEN_IRQHandler(void);\r
 void TIMER0_IRQHandler(void);\r
@@ -101,9 +101,9 @@ void AES_IRQHandler(void);
 void EBI_IRQHandler(void);\r
 void EMU_IRQHandler(void);\r
 void FPUEH_IRQHandler(void);\r
-#endif\r
 \r
 uint32_t SystemCoreClockGet(void);\r
+uint32_t SystemMaxCoreClockGet(void);\r
 \r
 /**************************************************************************//**\r
  * @brief\r
@@ -136,4 +136,4 @@ void SystemLFXOClockSet(uint32_t freq);
 #ifdef __cplusplus\r
 }\r
 #endif\r
-#endif /* __SYSTEM_EFM32WG_H */\r
+#endif /* SYSTEM_EFM32WG_H */\r