--- /dev/null
+/***************************************************************************//**\r
+ * @file em_dac.h\r
+ * @brief Digital to Analog Converter (DAC) peripheral API\r
+ * @version 4.0.0\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __EM_DAC_H\r
+#define __EM_DAC_H\r
+\r
+#include "em_device.h"\r
+#include "em_assert.h"\r
+\r
+#if defined(DAC_COUNT) && (DAC_COUNT > 0)\r
+\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup DAC\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+\r
+/** Validation of DAC register block pointer reference for assert statements. */\r
+#define DAC_REF_VALID(ref) ((ref) == DAC0)\r
+\r
+/** @endcond */\r
+\r
+/*******************************************************************************\r
+ ******************************** ENUMS ************************************\r
+ ******************************************************************************/\r
+\r
+/** Conversion mode. */\r
+typedef enum\r
+{\r
+ dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS, /**< Continuous mode. */\r
+ dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD, /**< Sample/hold mode. */\r
+ dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */\r
+} DAC_ConvMode_TypeDef;\r
+\r
+/** Output mode. */\r
+typedef enum\r
+{\r
+ dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE, /**< Output to pin and ADC disabled. */\r
+ dacOutputPin = _DAC_CTRL_OUTMODE_PIN, /**< Output to pin only. */\r
+ dacOutputADC = _DAC_CTRL_OUTMODE_ADC, /**< Output to ADC only */\r
+ dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC /**< Output to pin and ADC. */\r
+} DAC_Output_TypeDef;\r
+\r
+\r
+/** Peripheral Reflex System signal used to trigger single sample. */\r
+typedef enum\r
+{\r
+ dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */\r
+ dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
+ dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
+ dacPRSSELCh3 = _DAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH4 )\r
+ dacPRSSELCh4 = _DAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH5 )\r
+ dacPRSSELCh5 = _DAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH6 )\r
+ dacPRSSELCh6 = _DAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH7 )\r
+ dacPRSSELCh7 = _DAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH8 )\r
+ dacPRSSELCh8 = _DAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH9 )\r
+ dacPRSSELCh9 = _DAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH10 )\r
+ dacPRSSELCh10 = _DAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */\r
+#endif\r
+#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH11 )\r
+ dacPRSSELCh11 = _DAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */\r
+#endif\r
+} DAC_PRSSEL_TypeDef;\r
+\r
+\r
+/** Reference voltage for DAC. */\r
+typedef enum\r
+{\r
+ dacRef1V25 = _DAC_CTRL_REFSEL_1V25, /**< Internal 1.25V bandgap reference. */\r
+ dacRef2V5 = _DAC_CTRL_REFSEL_2V5, /**< Internal 2.5V bandgap reference. */\r
+ dacRefVDD = _DAC_CTRL_REFSEL_VDD /**< VDD reference. */\r
+} DAC_Ref_TypeDef;\r
+\r
+\r
+/** Refresh interval. */\r
+typedef enum\r
+{\r
+ dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES, /**< Refresh every 8 prescaled cycles. */\r
+ dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES, /**< Refresh every 16 prescaled cycles. */\r
+ dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES, /**< Refresh every 32 prescaled cycles. */\r
+ dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES /**< Refresh every 64 prescaled cycles. */\r
+} DAC_Refresh_TypeDef;\r
+\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/** DAC init structure, common for both channels. */\r
+typedef struct\r
+{\r
+ /** Refresh interval. Only used if REFREN bit set for a DAC channel. */\r
+ DAC_Refresh_TypeDef refresh;\r
+\r
+ /** Reference voltage to use. */\r
+ DAC_Ref_TypeDef reference;\r
+\r
+ /** Output mode */\r
+ DAC_Output_TypeDef outMode;\r
+\r
+ /** Conversion mode. */\r
+ DAC_ConvMode_TypeDef convMode;\r
+\r
+ /**\r
+ * Prescaler used to get DAC clock. Derived as follows:\r
+ * DACclk=HFPERclk/(2^prescale). The DAC clock should be <= 1MHz.\r
+ */\r
+ uint8_t prescale;\r
+\r
+ /** Enable/disable use of low pass filter on output. */\r
+ bool lpEnable;\r
+\r
+ /** Enable/disable reset of prescaler on ch0 start. */\r
+ bool ch0ResetPre;\r
+\r
+ /** Enable/disable output enable control by CH1 PRS signal. */\r
+ bool outEnablePRS;\r
+\r
+ /** Enable/disable sine mode. */\r
+ bool sineEnable;\r
+\r
+ /** Select if single ended or differential mode. */\r
+ bool diff;\r
+} DAC_Init_TypeDef;\r
+\r
+/** Default config for DAC init structure. */\r
+#define DAC_INIT_DEFAULT \\r
+ { dacRefresh8, /* Refresh every 8 prescaled cycles. */ \\r
+ dacRef1V25, /* 1.25V internal reference. */ \\r
+ dacOutputPin, /* Output to pin only. */ \\r
+ dacConvModeContinuous, /* Continuous mode. */ \\r
+ 0, /* No prescaling. */ \\r
+ false, /* Do not enable low pass filter. */ \\r
+ false, /* Do not reset prescaler on ch0 start. */ \\r
+ false, /* DAC output enable always on. */ \\r
+ false, /* Disable sine mode. */ \\r
+ false /* Single ended mode. */ \\r
+ }\r
+\r
+\r
+/** DAC channel init structure. */\r
+typedef struct\r
+{\r
+ /** Enable channel. */\r
+ bool enable;\r
+\r
+ /**\r
+ * Peripheral reflex system trigger enable. If false, channel is triggered\r
+ * by writing to CHnDATA.\r
+ */\r
+ bool prsEnable;\r
+\r
+ /**\r
+ * Enable/disable automatic refresh of channel. Refresh interval must be\r
+ * defined in common control init, please see DAC_Init().\r
+ */\r
+ bool refreshEnable;\r
+\r
+ /**\r
+ * Peripheral reflex system trigger selection. Only applicable if @p prsEnable\r
+ * is enabled.\r
+ */\r
+ DAC_PRSSEL_TypeDef prsSel;\r
+} DAC_InitChannel_TypeDef;\r
+\r
+/** Default config for DAC channel init structure. */\r
+#define DAC_INITCHANNEL_DEFAULT \\r
+ { false, /* Leave channel disabled when init done. */ \\r
+ false, /* Disable PRS triggering. */ \\r
+ false, /* Channel not refreshed automatically. */ \\r
+ dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \\r
+ }\r
+\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable);\r
+void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init);\r
+void DAC_InitChannel(DAC_TypeDef *dac,\r
+ const DAC_InitChannel_TypeDef *init,\r
+ unsigned int ch);\r
+void DAC_ChannelOutputSet(DAC_TypeDef *dac,\r
+ unsigned int channel,\r
+ uint32_t value);\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the output signal of DAC channel 0 to a given value.\r
+ *\r
+ * @details\r
+ * This function sets the output signal of DAC channel 0 by writing @p value\r
+ * to the CH0DATA register.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] value\r
+ * Value to write to the channel 0 output register CH0DATA.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,\r
+ uint32_t value )\r
+{\r
+ EFM_ASSERT(value<=_DAC_CH0DATA_MASK);\r
+ dac->CH0DATA = value;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the output signal of DAC channel 1 to a given value.\r
+ *\r
+ * @details\r
+ * This function sets the output signal of DAC channel 1 by writing @p value\r
+ * to the CH1DATA register.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] value\r
+ * Value to write to the channel 1 output register CH1DATA.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_Channel1OutputSet( DAC_TypeDef *dac,\r
+ uint32_t value )\r
+{\r
+ EFM_ASSERT(value<=_DAC_CH1DATA_MASK);\r
+ dac->CH1DATA = value;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending DAC interrupts.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * Pending DAC interrupt source to clear. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the DAC module (DAC_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)\r
+{\r
+ dac->IFC = flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more DAC interrupts.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * DAC interrupt sources to disable. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the DAC module (DAC_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)\r
+{\r
+ dac->IEN &= ~(flags);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more DAC interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using DAC_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * DAC interrupt sources to enable. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the DAC module (DAC_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)\r
+{\r
+ dac->IEN |= flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending DAC interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @return\r
+ * DAC interrupt sources pending. A bitwise logic OR combination of valid\r
+ * interrupt flags for the DAC module (DAC_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)\r
+{\r
+ return(dac->IF);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending DAC interrupts from SW.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * DAC interrupt sources to set to pending. Use a bitwise logic OR combination\r
+ * of valid interrupt flags for the DAC module (DAC_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DAC_IntSet(DAC_TypeDef *dac, uint32_t flags)\r
+{\r
+ dac->IFS = flags;\r
+}\r
+\r
+uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq);\r
+void DAC_Reset(DAC_TypeDef *dac);\r
+\r
+/** @} (end addtogroup DAC) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */\r
+\r
+#endif /* __EM_DAC_H */\r
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