/***************************************************************************//**\r
* @file em_gpio.h\r
* @brief General Purpose IO (GPIO) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#ifndef __SILICON_LABS_EM_GPIO_H_\r
-#define __SILICON_LABS_EM_GPIO_H_\r
+#ifndef __SILICON_LABS_EM_GPIO_H__\r
+#define __SILICON_LABS_EM_GPIO_H__\r
\r
#include "em_device.h"\r
#if defined(GPIO_COUNT) && (GPIO_COUNT > 0)\r
\r
#include <stdbool.h>\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
#include "em_assert.h"\r
\r
#ifdef __cplusplus\r
* @{\r
******************************************************************************/\r
\r
+/*******************************************************************************\r
+ ******************************* DEFINES ***********************************\r
+ ******************************************************************************/\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 14\r
+#define _GPIO_PORT_B_PIN_COUNT 10\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 9\r
+#define _GPIO_PORT_E_PIN_COUNT 12\r
+#define _GPIO_PORT_F_PIN_COUNT 6\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xF77F\r
+#define _GPIO_PORT_B_PIN_MASK 0x79F8\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0x01FF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFF0\r
+#define _GPIO_PORT_F_PIN_MASK 0x003F\r
+\r
+#elif defined( _EFM32_HAPPY_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 12\r
+#define _GPIO_PORT_D_PIN_COUNT 4\r
+#define _GPIO_PORT_E_PIN_COUNT 4\r
+#define _GPIO_PORT_F_PIN_COUNT 6\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x0707\r
+#define _GPIO_PORT_B_PIN_MASK 0x6980\r
+#define _GPIO_PORT_C_PIN_MASK 0xEF1F\r
+#define _GPIO_PORT_D_PIN_MASK 0x00F0\r
+#define _GPIO_PORT_E_PIN_MASK 0x3C00\r
+#define _GPIO_PORT_F_PIN_MASK 0x003F\r
+\r
+#elif defined( _EFM32_GIANT_FAMILY ) \\r
+ || defined( _EFM32_WONDER_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 16\r
+#define _GPIO_PORT_B_PIN_COUNT 16\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 16\r
+#define _GPIO_PORT_E_PIN_COUNT 16\r
+#define _GPIO_PORT_F_PIN_COUNT 13\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_F_PIN_MASK 0x1FFF\r
+\r
+#elif defined( _EFM32_GECKO_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 16\r
+#define _GPIO_PORT_B_PIN_COUNT 16\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 16\r
+#define _GPIO_PORT_E_PIN_COUNT 16\r
+#define _GPIO_PORT_F_PIN_COUNT 10\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_F_PIN_MASK 0x03FF\r
+\r
+#elif defined( _EFR32_MIGHTY_FAMILY ) \\r
+ || defined( _EFR32_BLUE_FAMILY ) \\r
+ || defined( _EFR32_FLEX_FAMILY ) \\r
+ || defined( _EFR32_ZAPPY_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 6\r
+#define _GPIO_PORT_D_PIN_COUNT 3\r
+#define _GPIO_PORT_E_PIN_COUNT 0\r
+#define _GPIO_PORT_F_PIN_COUNT 8\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x003F\r
+#define _GPIO_PORT_B_PIN_MASK 0xF800\r
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0\r
+#define _GPIO_PORT_D_PIN_MASK 0xE000\r
+#define _GPIO_PORT_E_PIN_MASK 0x0000\r
+#define _GPIO_PORT_F_PIN_MASK 0x00FF\r
+\r
+#elif defined( _EFM32_PEARL_FAMILY ) \\r
+ || defined( _EFM32_JADE_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 6\r
+#define _GPIO_PORT_D_PIN_COUNT 7\r
+#define _GPIO_PORT_E_PIN_COUNT 0\r
+#define _GPIO_PORT_F_PIN_COUNT 8\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x003F\r
+#define _GPIO_PORT_B_PIN_MASK 0xF800\r
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0\r
+#define _GPIO_PORT_D_PIN_MASK 0xFE00\r
+#define _GPIO_PORT_E_PIN_MASK 0x0000\r
+#define _GPIO_PORT_F_PIN_MASK 0x00FF\r
+\r
+#else\r
+#warning "Port and pin masks are not defined for this family."\r
+#endif\r
+\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )\r
+#define _GPIO_PORT_SIZE(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \\r
+ (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \\r
+ (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \\r
+ 0)\r
+#else\r
+#define _GPIO_PORT_SIZE(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \\r
+ 0)\r
+#endif\r
+\r
+#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK )\r
+#define _GPIO_PORT_MASK(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \\r
+ (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \\r
+ (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \\r
+ 0)\r
+#else\r
+#define _GPIO_PORT_MASK(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \\r
+ 0)\r
+#endif\r
+\r
+/** Validation of port and pin */\r
+#define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) )\r
+#define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )\r
+\r
+/** Highest GPIO pin number */\r
+#define GPIO_PIN_MAX 15\r
+\r
+/** Highest GPIO port number */\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )\r
+#define GPIO_PORT_MAX 7\r
+#else\r
+#define GPIO_PORT_MAX 5\r
+#endif\r
+/** @endcond */\r
+\r
/*******************************************************************************\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
-/** GPIO ports identificator. */\r
+/** GPIO ports ids. */\r
typedef enum\r
{\r
- gpioPortA = 0, /**< Port A */\r
- gpioPortB = 1, /**< Port B */\r
- gpioPortC = 2, /**< Port C */\r
- gpioPortD = 3, /**< Port D */\r
- gpioPortE = 4, /**< Port E */\r
- gpioPortF = 5 /**< Port F */\r
+#if ( _GPIO_PORT_A_PIN_COUNT > 0 )\r
+ gpioPortA = 0,\r
+#endif\r
+#if ( _GPIO_PORT_B_PIN_COUNT > 0 )\r
+ gpioPortB = 1,\r
+#endif\r
+#if ( _GPIO_PORT_C_PIN_COUNT > 0 )\r
+ gpioPortC = 2,\r
+#endif\r
+#if ( _GPIO_PORT_D_PIN_COUNT > 0 )\r
+ gpioPortD = 3,\r
+#endif\r
+#if ( _GPIO_PORT_E_PIN_COUNT > 0 )\r
+ gpioPortE = 4,\r
+#endif\r
+#if ( _GPIO_PORT_F_PIN_COUNT > 0 )\r
+ gpioPortF = 5\r
+#endif\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )\r
+ gpioPortG = 6\r
+#endif\r
+#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )\r
+ gpioPortH = 7\r
+#endif\r
} GPIO_Port_TypeDef;\r
\r
+#if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )\r
/** GPIO drive mode. */\r
typedef enum\r
{\r
/** 2 mA */\r
gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW\r
} GPIO_DriveMode_TypeDef;\r
+#endif\r
+\r
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )\r
+/** GPIO drive strength. */\r
+typedef enum\r
+{\r
+ /** GPIO weak 1mA and alternate function weak 1mA */\r
+ gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,\r
+\r
+ /** GPIO weak 1mA and alternate function strong 10mA */\r
+ gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,\r
\r
-/** Pin mode. For more details on each mode, please refer to the EFM32\r
+ /** GPIO strong 10mA and alternate function weak 1mA */\r
+ gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,\r
+\r
+ /** GPIO strong 10mA and alternate function strong 10mA */\r
+ gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,\r
+} GPIO_DriveStrength_TypeDef;\r
+/* For legacy support */\r
+#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong\r
+#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak\r
+#endif\r
+\r
+/** Pin mode. For more details on each mode, please refer to the\r
* reference manual. */\r
typedef enum\r
{\r
gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER,\r
/** Push-pull output */\r
gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL,\r
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )\r
/** Push-pull output with drive-strength set by DRIVEMODE */\r
gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,\r
+#endif\r
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )\r
+ /** Push-pull using alternate control */\r
+ gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT,\r
+#endif\r
/** Wired-or output */\r
- gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR,\r
+ gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR,\r
/** Wired-or output with pull-down */\r
- gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,\r
+ gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,\r
/** Open-drain output */\r
- gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND,\r
+ gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND,\r
/** Open-drain output with filter */\r
- gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,\r
+ gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,\r
/** Open-drain output with pullup */\r
- gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,\r
+ gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,\r
/** Open-drain output with filter and pullup */\r
- gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,\r
+ gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,\r
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )\r
/** Open-drain output with drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,\r
+ gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,\r
/** Open-drain output with filter and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,\r
+ gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,\r
/** Open-drain output with pullup and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,\r
+ gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,\r
/** Open-drain output with filter, pullup and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER\r
+ gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER\r
+#endif\r
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )\r
+ /** Open-drain output using alternate control */\r
+ gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT,\r
+ /** Open-drain output using alternate control with filter */\r
+ gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER,\r
+ /** Open-drain output using alternate control with pullup */\r
+ gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP,\r
+ /** Open-drain output uisng alternate control with filter and pullup */\r
+ gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER,\r
+#endif\r
} GPIO_Mode_TypeDef;\r
\r
-\r
-/*******************************************************************************\r
- ******************************* DEFINES ***********************************\r
- ******************************************************************************/\r
-\r
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-\r
-/** Validation of pin typically usable in assert statements. */\r
-#define GPIO_PIN_VALID(pin) ((pin) < 16)\r
-\r
-/** Validation of port typically usable in assert statements. */\r
-#define GPIO_PORT_VALID(port) ((port) <= gpioPortF)\r
-\r
-/** @endcond */\r
-\r
-\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
GPIO_Mode_TypeDef mode,\r
unsigned int out);\r
\r
-# if defined( GPIO_CTRL_EM4RET )\r
-__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable);\r
+# if defined( _GPIO_EM4WUEN_MASK )\r
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);\r
#endif\r
\r
/***************************************************************************//**\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWCLKPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWCLK pin is not defined."\r
+#endif\r
}\r
\r
\r
/***************************************************************************//**\r
* @brief\r
- * Enable/disable serial wire data pin.\r
+ * Enable/disable serial wire data I/O pin.\r
*\r
* @note\r
* Disabling SWDClk will disable the debug interface, which may result in\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWDIOPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWDIO pin is not defined."\r
+#endif\r
}\r
\r
\r
-#if defined( GPIO_ROUTE_SWOPEN )\r
+#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Enable/Disable serial wire output pin.\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWOPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWO/SWV pin is not defined."\r
+#endif\r
}\r
#endif\r
\r
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)\r
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);\r
+#endif\r
\r
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )\r
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength);\r
+#endif\r
\r
# if defined( _GPIO_EM4WUEN_MASK )\r
/**************************************************************************//**\r
#endif\r
\r
\r
-# if defined( _GPIO_EM4WUEN_MASK )\r
-/**************************************************************************//**\r
- * @brief\r
- * Enable GPIO pin wake-up from EM4. When the function exits,\r
- * EM4 mode can be safely entered.\r
- *\r
- * @note\r
- * It is assumed that the GPIO pin modes are set correctly.\r
- * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.\r
- *\r
- * @param[in] pinmask\r
- * Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.\r
- * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
- * @param[in] polaritymask\r
- * Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.\r
- * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
- *****************************************************************************/\r
-__STATIC_INLINE void GPIO_EM4EnablePinWakeup(uint32_t pinmask,\r
- uint32_t polaritymask)\r
-{\r
- EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);\r
- EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);\r
-\r
- GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */\r
- GPIO->EM4WUPOL |= pinmask & polaritymask;\r
- GPIO->EM4WUEN |= pinmask; /* Enable wakeup */\r
-\r
- GPIO_EM4SetPinRetention(true); /* Enable pin retention */\r
-\r
- GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */\r
-}\r
-#endif\r
-\r
-#if defined( _GPIO_EM4WUCAUSE_MASK )\r
+#if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _RMU_RSTCAUSE_EM4RST_MASK )\r
/**************************************************************************//**\r
* @brief\r
* Check which GPIO pin(s) that caused a wake-up from EM4.\r
*****************************************************************************/\r
__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)\r
{\r
+#if defined( _GPIO_EM4WUCAUSE_MASK )\r
return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;\r
+#else\r
+ return RMU->RSTCAUSE & _RMU_RSTCAUSE_EM4RST_MASK;\r
+#endif\r
}\r
#endif\r
\r
\r
-# if defined( GPIO_CTRL_EM4RET )\r
+#if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )\r
/**************************************************************************//**\r
* @brief\r
* Enable GPIO pin retention of output enable, output value, pull enable and\r
* pull direction in EM4.\r
+ * \r
+ * @note\r
+ * For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers \r
+ * more pin retention features. This function implements the EM4EXIT retention\r
+ * mode on platform 2.\r
*\r
* @param[in] enable\r
* @li true - enable EM4 pin retention.\r
{\r
if (enable)\r
{\r
+#if defined( GPIO_CTRL_EM4RET )\r
GPIO->CTRL |= GPIO_CTRL_EM4RET;\r
+#else\r
+ EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)\r
+ | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;\r
+#endif\r
}\r
else\r
{\r
+#if defined( GPIO_CTRL_EM4RET )\r
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;\r
+#else\r
+ EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)\r
+ | EMU_EM4CTRL_EM4IORETMODE_DISABLE;\r
+#endif\r
}\r
}\r
#endif\r
* @li GPIO_INSENSE_PRS - peripheral reflex system input sensing.\r
*\r
* @param[in] mask\r
- * Mask containing bitwise logic OR of bits similar as for @p val used to indicate\r
- * which input sense options to disable/enable.\r
+ * Mask containing bitwise logic OR of bits similar as for @p val used to\r
+ * indicate which input sense options to disable/enable.\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)\r
{\r
******************************************************************************/\r
__STATIC_INLINE uint32_t GPIO_IntGet(void)\r
{\r
- return(GPIO->IF);\r
+ return GPIO->IF;\r
}\r
\r
\r
* @return\r
* The pin value, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, unsigned int pin)\r
+__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port,\r
+ unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
- return((unsigned int)((GPIO->P[port].DIN >> pin) & 0x1));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+ return BUS_RegBitRead(&GPIO->P[port].DIN, pin);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+#if defined( _GPIO_P_DOUTCLR_MASK )\r
GPIO->P[port].DOUTCLR = 1 << pin;\r
+#else\r
+ BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);\r
+#endif\r
}\r
\r
\r
* @return\r
* The DOUT setting for the requested pin, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, unsigned int pin)\r
+__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port,\r
+ unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
- return((unsigned int)((GPIO->P[port].DOUT >> pin) & 0x1));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+ return BUS_RegBitRead(&GPIO->P[port].DOUT, pin);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+#if defined( _GPIO_P_DOUTSET_MASK )\r
GPIO->P[port].DOUTSET = 1 << pin;\r
+#else\r
+ BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);\r
+#endif\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
\r
GPIO->P[port].DOUTTGL = 1 << pin;\r
}\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- return(GPIO->P[port].DIN & _GPIO_P_DIN_DIN_MASK);\r
+ return GPIO->P[port].DIN;\r
}\r
\r
\r
__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
-\r
- GPIO->P[port].DOUTCLR = pins & _GPIO_P_DOUTCLR_DOUTCLR_MASK;\r
+#if defined( _GPIO_P_DOUTCLR_MASK )\r
+ GPIO->P[port].DOUTCLR = pins;\r
+#else\r
+ BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);\r
+#endif\r
}\r
\r
\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- return(GPIO->P[port].DOUT & _GPIO_P_DOUT_DOUT_MASK);\r
+ return GPIO->P[port].DOUT;\r
}\r
\r
\r
__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
-\r
- GPIO->P[port].DOUTSET = pins & _GPIO_P_DOUTSET_DOUTSET_MASK;\r
+#if defined( _GPIO_P_DOUTSET_MASK )\r
+ GPIO->P[port].DOUTSET = pins;\r
+#else\r
+ BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);\r
+#endif\r
}\r
\r
\r
* @param[in] mask\r
* Mask indicating which bits to modify.\r
******************************************************************************/\r
-__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, uint32_t val, uint32_t mask)\r
+__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port,\r
+ uint32_t val,\r
+ uint32_t mask)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
\r
/***************************************************************************//**\r
* @brief\r
- * Toggle a single pin in GPIO port data out register.\r
+ * Toggle pins in GPIO port data out register.\r
*\r
* @note\r
* In order for the setting to take effect on the output pad, the pin must\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- GPIO->P[port].DOUTTGL = pins & _GPIO_P_DOUTTGL_DOUTTGL_MASK;\r
+ GPIO->P[port].DOUTTGL = pins;\r
}\r
\r
\r
GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK;\r
}\r
\r
-\r
/** @} (end addtogroup GPIO) */\r
/** @} (end addtogroup EM_Library) */\r
\r
#endif\r
\r
#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_GPIO_H_ */\r
+#endif /* __SILICON_LABS_EM_GPIO_H__ */\r
projects / freertos / blobdiff