--- /dev/null
+/***************************************************************************//**\r
+ * @file em_mpu.h\r
+ * @brief Memory protection unit (MPU) peripheral API\r
+ * @version 4.0.0\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SILICON_LABS_EM_MPU_H_\r
+#define __SILICON_LABS_EM_MPU_H_\r
+\r
+#include "em_device.h"\r
+\r
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+#include "em_assert.h"\r
+\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup MPU\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/** @anchor MPU_CTRL_PRIVDEFENA\r
+ * Argument to MPU_enable(). Enables priviledged\r
+ * access to default memory map. */\r
+#define MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk\r
+\r
+/** @anchor MPU_CTRL_HFNMIENA\r
+ * Argument to MPU_enable(). Enables MPU during hard fault,\r
+ * NMI, and FAULTMASK handlers. */\r
+#define MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk\r
+\r
+/*******************************************************************************\r
+ ******************************** ENUMS ************************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * Size of an MPU region.\r
+ */\r
+typedef enum\r
+{\r
+ mpuRegionSize32b = 4, /**< 32 byte region size. */\r
+ mpuRegionSize64b = 5, /**< 64 byte region size. */\r
+ mpuRegionSize128b = 6, /**< 128 byte region size. */\r
+ mpuRegionSize256b = 7, /**< 256 byte region size. */\r
+ mpuRegionSize512b = 8, /**< 512 byte region size. */\r
+ mpuRegionSize1Kb = 9, /**< 1K byte region size. */\r
+ mpuRegionSize2Kb = 10, /**< 2K byte region size. */\r
+ mpuRegionSize4Kb = 11, /**< 4K byte region size. */\r
+ mpuRegionSize8Kb = 12, /**< 8K byte region size. */\r
+ mpuRegionSize16Kb = 13, /**< 16K byte region size. */\r
+ mpuRegionSize32Kb = 14, /**< 32K byte region size. */\r
+ mpuRegionSize64Kb = 15, /**< 64K byte region size. */\r
+ mpuRegionSize128Kb = 16, /**< 128K byte region size. */\r
+ mpuRegionSize256Kb = 17, /**< 256K byte region size. */\r
+ mpuRegionSize512Kb = 18, /**< 512K byte region size. */\r
+ mpuRegionSize1Mb = 19, /**< 1M byte region size. */\r
+ mpuRegionSize2Mb = 20, /**< 2M byte region size. */\r
+ mpuRegionSize4Mb = 21, /**< 4M byte region size. */\r
+ mpuRegionSize8Mb = 22, /**< 8M byte region size. */\r
+ mpuRegionSize16Mb = 23, /**< 16M byte region size. */\r
+ mpuRegionSize32Mb = 24, /**< 32M byte region size. */\r
+ mpuRegionSize64Mb = 25, /**< 64M byte region size. */\r
+ mpuRegionSize128Mb = 26, /**< 128M byte region size. */\r
+ mpuRegionSize256Mb = 27, /**< 256M byte region size. */\r
+ mpuRegionSize512Mb = 28, /**< 512M byte region size. */\r
+ mpuRegionSize1Gb = 29, /**< 1G byte region size. */\r
+ mpuRegionSize2Gb = 30, /**< 2G byte region size. */\r
+ mpuRegionSize4Gb = 31 /**< 4G byte region size. */\r
+} MPU_RegionSize_TypeDef;\r
+\r
+/**\r
+ * MPU region access permission attributes.\r
+ */\r
+typedef enum\r
+{\r
+ mpuRegionNoAccess = 0, /**< No access what so ever. */\r
+ mpuRegionApPRw = 1, /**< Priviledged state R/W only. */\r
+ mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */\r
+ mpuRegionApFullAccess = 3, /**< R/W in Priviledged and User state. */\r
+ mpuRegionApPRo = 5, /**< Priviledged R only. */\r
+ mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */\r
+} MPU_RegionAp_TypeDef;\r
+\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/** MPU Region init structure. */\r
+typedef struct\r
+{\r
+ bool regionEnable; /**< MPU region enable. */\r
+ uint8_t regionNo; /**< MPU region number. */\r
+ uint32_t baseAddress; /**< Region baseaddress. */\r
+ MPU_RegionSize_TypeDef size; /**< Memory region size. */\r
+ MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */\r
+ bool disableExec; /**< Disable execution. */\r
+ bool shareable; /**< Memory shareable attribute. */\r
+ bool cacheable; /**< Memory cacheable attribute. */\r
+ bool bufferable; /**< Memory bufferable attribute. */\r
+ uint8_t srd; /**< Memory subregion disable bits. */\r
+ uint8_t tex; /**< Memory type extension attributes. */\r
+} MPU_RegionInit_TypeDef;\r
+\r
+/** Default configuration of MPU region init structure for flash memory. */\r
+#define MPU_INIT_FLASH_DEFAULT \\r
+ { \\r
+ true, /* Enable MPU region. */ \\r
+ 0, /* MPU Region number. */ \\r
+ FLASH_MEM_BASE, /* Flash base address. */ \\r
+ mpuRegionSize1Mb, /* Size - Set to max. */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ false, /* Execution allowed. */ \\r
+ false, /* Not shareable. */ \\r
+ true, /* Cacheable. */ \\r
+ false, /* Not bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+ }\r
+\r
+\r
+/** Default configuration of MPU region init structure for sram memory. */\r
+#define MPU_INIT_SRAM_DEFAULT \\r
+ { \\r
+ true, /* Enable MPU region. */ \\r
+ 1, /* MPU Region number. */ \\r
+ RAM_MEM_BASE, /* SRAM base address. */ \\r
+ mpuRegionSize128Kb, /* Size - Set to max. */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ false, /* Execution allowed. */ \\r
+ true, /* Shareable. */ \\r
+ true, /* Cacheable. */ \\r
+ false, /* Not bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+ }\r
+\r
+\r
+/** Default configuration of MPU region init structure for onchip peripherals.*/\r
+#define MPU_INIT_PERIPHERAL_DEFAULT \\r
+ { \\r
+ true, /* Enable MPU region. */ \\r
+ 0, /* MPU Region number. */ \\r
+ 0, /* Region base address. */ \\r
+ mpuRegionSize32b, /* Size - Set to minimum */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ true, /* Execution not allowed. */ \\r
+ true, /* Shareable. */ \\r
+ false, /* Not cacheable. */ \\r
+ true, /* Bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+ }\r
+\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+\r
+void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable the MPU\r
+ * @details\r
+ * Disable MPU and MPU fault exceptions.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void MPU_Disable(void)\r
+{\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable the MPU\r
+ * @details\r
+ * Enable MPU and MPU fault exceptions.\r
+ * @param[in] flags\r
+ * Use a logical OR of @ref MPU_CTRL_PRIVDEFENA and\r
+ * @ref MPU_CTRL_HFNMIENA as needed.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void MPU_Enable(uint32_t flags)\r
+{\r
+ EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk |\r
+ MPU_CTRL_HFNMIENA_Msk |\r
+ MPU_CTRL_ENABLE_Msk)));\r
+\r
+ MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */\r
+}\r
+\r
+\r
+/** @} (end addtogroup MPU) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */\r
+\r
+#endif /* __SILICON_LABS_EM_MPU_H_ */\r
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