/*\r
- FreeRTOS V9.0.0rc1 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
__asm volatile\r
(\r
".extern ulRegTest1LoopCounter \n"\r
- "/* Fill the core registers with known values. */ \n"\r
- "mov r0, #100 \n"\r
- "mov r1, #101 \n"\r
- "mov r2, #102 \n"\r
- "mov r3, #103 \n"\r
- "mov r4, #104 \n"\r
- "mov r5, #105 \n"\r
- "mov r6, #106 \n"\r
- "mov r7, #107 \n"\r
- "mov r8, #108 \n"\r
- "mov r9, #109 \n"\r
- "mov r10, #110 \n"\r
- "mov r11, #111 \n"\r
- "mov r12, #112 \n"\r
-\r
- "reg1_loop: \n"\r
-\r
- "/* Check each register has maintained its expected value. */ \n"\r
- "cmp r0, #100 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r1, #101 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r2, #102 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r3, #103 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r4, #104 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r5, #105 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r6, #106 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r7, #107 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r8, #108 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r9, #109 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r10, #110 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r11, #111 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r12, #112 \n"\r
- "bne reg1_error_loop \n"\r
-\r
- "/* Everything passed, increment the loop counter. */ \n"\r
- "push { r0-r1 } \n"\r
+\r
+ /* Fill the core registers with known values. */\r
+ "mov r0, #100 \n"\r
+ "mov r1, #101 \n"\r
+ "mov r2, #102 \n"\r
+ "mov r3, #103 \n"\r
+ "mov r4, #104 \n"\r
+ "mov r5, #105 \n"\r
+ "mov r6, #106 \n"\r
+ "mov r7, #107 \n"\r
+ "mov r8, #108 \n"\r
+ "mov r9, #109 \n"\r
+ "mov r10, #110 \n"\r
+ "mov r11, #111 \n"\r
+ "mov r12, #112 \n"\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg1_loop: \n"\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ "pop {r0-r1} \n"\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ "b reg1_loopf_pass \n"\r
+\r
+ "reg1_error_loopf: \n"\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ "b reg1_error_loopf \n"\r
+\r
+ "reg1_loopf_pass: \n"\r
+\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r2, #102 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r3, #103 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r4, #104 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r5, #105 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r6, #106 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r7, #107 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r8, #108 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r9, #109 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r10, #110 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r11, #111 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r12, #112 \n"\r
+ "bne reg1_error_loop \n"\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ "push { r0-r1 } \n"\r
"ldr r0, =ulRegTest1LoopCounter \n"\r
- "ldr r1, [r0] \n"\r
- "adds r1, r1, #1 \n"\r
- "str r1, [r0] \n"\r
- "pop { r0-r1 } \n"\r
-\r
- "/* Start again. */ \n"\r
- "b reg1_loop \n"\r
-\r
- "reg1_error_loop: \n"\r
- "/* If this line is hit then there was an error in a core register value. \n"\r
- "The loop ensures the loop counter stops incrementing. */ \n"\r
- "b reg1_error_loop \n"\r
- "nop "\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+ "pop { r0-r1 } \n"\r
+\r
+ /* Start again. */\r
+ "b reg1_loop \n"\r
+\r
+ "reg1_error_loop: \n"\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ "b reg1_error_loop \n"\r
+ "nop \n"\r
); /* __asm volatile. */\r
}\r
/*-----------------------------------------------------------*/\r
{\r
__asm volatile\r
(\r
- ".extern ulRegTest2LoopCounter \n"\r
- "/* Set all the core registers to known values. */ \n"\r
- "mov r0, #-1 \n"\r
- "mov r1, #1 \n"\r
- "mov r2, #2 \n"\r
- "mov r3, #3 \n"\r
- "mov r4, #4 \n"\r
- "mov r5, #5 \n"\r
- "mov r6, #6 \n"\r
- "mov r7, #7 \n"\r
- "mov r8, #8 \n"\r
- "mov r9, #9 \n"\r
- "mov r10, #10 \n"\r
- "mov r11, #11 \n"\r
- "mov r12, #12 \n"\r
-\r
- "reg2_loop: \n"\r
-\r
- "cmp r0, #-1 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r1, #1 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r2, #2 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r3, #3 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r4, #4 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r5, #5 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r6, #6 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r7, #7 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r8, #8 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r9, #9 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r10, #10 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r11, #11 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r12, #12 \n"\r
- "bne reg2_error_loop \n"\r
-\r
- "/* Increment the loop counter to indicate this test is still functioning \n"\r
- "correctly. */ \n"\r
- "push { r0-r1 } \n"\r
+ ".extern ulRegTest2LoopCounter \n"\r
+\r
+ /* Set all the core registers to known values. */\r
+ "mov r0, #-1 \n"\r
+ "mov r1, #1 \n"\r
+ "mov r2, #2 \n"\r
+ "mov r3, #3 \n"\r
+ "mov r4, #4 \n"\r
+ "mov r5, #5 \n"\r
+ "mov r6, #6 \n"\r
+ "mov r7, #7 \n"\r
+ "mov r8, #8 \n"\r
+ "mov r9, #9 \n"\r
+ "mov r10, #10 \n"\r
+ "mov r11, #11 \n"\r
+ "mov r12, #12 \n"\r
+\r
+ /* Set all the VFP to known values. */\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg2_loop: \n"\r
+\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ "pop {r0-r1} \n"\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ "b reg2_loopf_pass \n"\r
+\r
+ "reg2_error_loopf: \n"\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ "b reg2_error_loopf \n"\r
+\r
+ "reg2_loopf_pass: \n"\r
+\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r2, #2 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r3, #3 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r4, #4 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r5, #5 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r6, #6 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r7, #7 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r8, #8 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r9, #9 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r10, #10 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r11, #11 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r12, #12 \n"\r
+ "bne reg2_error_loop \n"\r
+\r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ "push { r0-r1 } \n"\r
"ldr r0, =ulRegTest2LoopCounter \n"\r
- "ldr r1, [r0] \n"\r
- "adds r1, r1, #1 \n"\r
- "str r1, [r0] \n"\r
-\r
- "/* Yield to increase test coverage. */ \n"\r
- "movs r0, #0x01 \n"\r
- "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n"\r
- "lsl r0, r0, #28 /* Shift to PendSV bit */ \n"\r
- "str r0, [r1] \n"\r
- "dsb \n"\r
-\r
- "pop { r0-r1 } \n"\r
-\r
- "/* Start again. */ \n"\r
- "b reg2_loop \n"\r
-\r
- "reg2_error_loop: \n"\r
- "/* If this line is hit then there was an error in a core register value. \n"\r
- "This loop ensures the loop counter variable stops incrementing. */ \n"\r
- "b reg2_error_loop \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+\r
+ /* Yield to increase test coverage. */\r
+ "movs r0, #0x01 \n"\r
+ "ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */\r
+ "lsl r0, r0, #28 \n" /* Shift to PendSV bit */\r
+ "str r0, [r1] \n"\r
+ "dsb \n"\r
+\r
+ "pop { r0-r1 } \n"\r
+\r
+ /* Start again. */\r
+ "b reg2_loop \n"\r
+\r
+ "reg2_error_loop: \n"\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ "b reg2_error_loop \n"\r
+ \r
); /* __asm volatile */\r
}\r
/*-----------------------------------------------------------*/\r
projects / freertos / blobdiff