--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016 - 2019 , NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_CLOCK_H_\r
+#define _FSL_CLOCK_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*! @addtogroup clock */\r
+/*! @{ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ *****************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief CLOCK driver version 2.2.0. */\r
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))\r
+/*@}*/\r
+\r
+/* Definition for delay API in clock driver, users can redefine it to the real application. */\r
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY\r
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000UL)\r
+#endif\r
+\r
+/*!\r
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.\r
+ *\r
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function\r
+ * would cache the recent calulation and accelerate the execution to get the\r
+ * right settings.\r
+ */\r
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT\r
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U\r
+#endif\r
+\r
+/*! @brief Clock ip name array for FLEXCOMM. */\r
+#define FLEXCOMM_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \\r
+ kCLOCK_FlexComm6, kCLOCK_FlexComm7 \\r
+ }\r
+/*! @brief Clock ip name array for LPUART. */\r
+#define LPUART_CLOCKS \\r
+ { \\r
+ kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \\r
+ kCLOCK_MinUart6, kCLOCK_MinUart7 \\r
+ }\r
+\r
+/*! @brief Clock ip name array for BI2C. */\r
+#define BI2C_CLOCKS \\r
+ { \\r
+ kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \\r
+ }\r
+/*! @brief Clock ip name array for LSPI. */\r
+#define LPSI_CLOCKS \\r
+ { \\r
+ kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \\r
+ }\r
+/*! @brief Clock ip name array for FLEXI2S. */\r
+#define FLEXI2S_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \\r
+ kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \\r
+ }\r
+/*! @brief Clock ip name array for UTICK. */\r
+#define UTICK_CLOCKS \\r
+ { \\r
+ kCLOCK_Utick \\r
+ }\r
+/*! @brief Clock ip name array for DMA. */\r
+#define DMA_CLOCKS \\r
+ { \\r
+ kCLOCK_Dma \\r
+ }\r
+/*! @brief Clock ip name array for CT32B. */\r
+#define CTIMER_CLOCKS \\r
+ { \\r
+ kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer3 \\r
+ }\r
+\r
+/*! @brief Clock ip name array for GPIO. */\r
+#define GPIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio0, kCLOCK_Gpio1 \\r
+ }\r
+/*! @brief Clock ip name array for ADC. */\r
+#define ADC_CLOCKS \\r
+ { \\r
+ kCLOCK_Adc0 \\r
+ }\r
+/*! @brief Clock ip name array for MRT. */\r
+#define MRT_CLOCKS \\r
+ { \\r
+ kCLOCK_Mrt \\r
+ }\r
+/*! @brief Clock ip name array for MRT. */\r
+#define SCT_CLOCKS \\r
+ { \\r
+ kCLOCK_Sct0 \\r
+ }\r
+/*! @brief Clock ip name array for RTC. */\r
+#define RTC_CLOCKS \\r
+ { \\r
+ kCLOCK_Rtc \\r
+ }\r
+/*! @brief Clock ip name array for WWDT. */\r
+#define WWDT_CLOCKS \\r
+ { \\r
+ kCLOCK_Wwdt \\r
+ }\r
+/*! @brief Clock ip name array for CRC. */\r
+#define CRC_CLOCKS \\r
+ { \\r
+ kCLOCK_Crc \\r
+ }\r
+/*! @brief Clock ip name array for USBD. */\r
+#define USBD_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbd0 \\r
+ }\r
+\r
+/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */\r
+#define GINT_CLOCKS \\r
+ { \\r
+ kCLOCK_Gint, kCLOCK_Gint \\r
+ }\r
+\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+/*------------------------------------------------------------------------------\r
+ clock_ip_name_t definition:\r
+------------------------------------------------------------------------------*/\r
+\r
+#define CLK_GATE_REG_OFFSET_SHIFT 8U\r
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U\r
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U\r
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU\r
+\r
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \\r
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \\r
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))\r
+\r
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)\r
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)\r
+\r
+#define AHB_CLK_CTRL0 0\r
+#define AHB_CLK_CTRL1 1\r
+#define ASYNC_CLK_CTRL0 2\r
+\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+typedef enum _clock_ip_name\r
+{\r
+ kCLOCK_IpInvalid = 0U,\r
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),\r
+ kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),\r
+ kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),\r
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),\r
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),\r
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),\r
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),\r
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),\r
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */\r
+ kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),\r
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),\r
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),\r
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),\r
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),\r
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),\r
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),\r
+ kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),\r
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),\r
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),\r
+ kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),\r
+ kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),\r
+\r
+ kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),\r
+} clock_ip_name_t;\r
+\r
+/*! @brief Clock name used to get clock frequency. */\r
+typedef enum _clock_name\r
+{\r
+ kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */\r
+ kCLOCK_BusClk, /*!< Bus clock (AHB clock) */\r
+ kCLOCK_FroHf, /*!< FRO48/96 */\r
+ kCLOCK_Fro12M, /*!< FRO12M */\r
+ kCLOCK_ExtClk, /*!< External Clock */\r
+ kCLOCK_PllOut, /*!< PLL Output */\r
+ kCLOCK_UsbClk, /*!< USB input */\r
+ kCLOCK_WdtOsc, /*!< Watchdog Oscillator */\r
+ kCLOCK_Frg, /*!< Frg Clock */\r
+ kCLOCK_AsyncApbClk, /*!< Async APB clock */\r
+ kCLOCK_FlexI2S, /*!< FlexI2S clock */\r
+ kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */\r
+ kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */\r
+ kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */\r
+ kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */\r
+ kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */\r
+ kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */\r
+ kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */\r
+ kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */\r
+} clock_name_t;\r
+\r
+/**\r
+ * Clock source selections for the asynchronous APB clock\r
+ */\r
+typedef enum _async_clock_src\r
+{\r
+ kCLOCK_AsyncMainClk = 0, /*!< Main System clock */\r
+ kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */\r
+} async_clock_src_t;\r
+\r
+/*! @brief Clock Mux Switches\r
+ * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable\r
+ * starting from LSB upwards\r
+ *\r
+ * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*\r
+ *\r
+ */\r
+\r
+#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U))\r
+#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U)\r
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U))\r
+\r
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)\r
+#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)\r
+#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU)\r
+#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U)\r
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)\r
+\r
+#define CM_MAINCLKSELA 0\r
+#define CM_MAINCLKSELB 1\r
+#define CM_CLKOUTCLKSELA 2\r
+#define CM_CLKOUTCLKSELB 3\r
+#define CM_SYSPLLCLKSEL 4\r
+#define CM_USBPLLCLKSEL 5\r
+#define CM_AUDPLLCLKSEL 6\r
+#define CM_SCTPLLCLKSEL 7\r
+#define CM_ADCASYNCCLKSEL 9\r
+#define CM_USBCLKSEL 10\r
+#define CM_USB1CLKSEL 11\r
+#define CM_FXCOMCLKSEL0 12\r
+#define CM_FXCOMCLKSEL1 13\r
+#define CM_FXCOMCLKSEL2 14\r
+#define CM_FXCOMCLKSEL3 15\r
+#define CM_FXCOMCLKSEL4 16\r
+#define CM_FXCOMCLKSEL5 17\r
+#define CM_FXCOMCLKSEL6 18\r
+#define CM_FXCOMCLKSEL7 19\r
+#define CM_FXCOMCLKSEL8 20\r
+#define CM_FXCOMCLKSEL9 21\r
+#define CM_FXCOMCLKSEL10 22\r
+#define CM_FXCOMCLKSEL11 23\r
+#define CM_FXI2S0MCLKCLKSEL 24\r
+#define CM_FXI2S1MCLKCLKSEL 25\r
+#define CM_FRGCLKSEL 26\r
+\r
+#define CM_ASYNCAPB 28\r
+\r
+typedef enum _clock_attach_id\r
+{\r
+\r
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),\r
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),\r
+\r
+ kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),\r
+ kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),\r
+ kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),\r
+ kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),\r
+ kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),\r
+ kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),\r
+\r
+ kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),\r
+ kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),\r
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),\r
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),\r
+ kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),\r
+ kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),\r
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),\r
+ kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),\r
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),\r
+ kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),\r
+ kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),\r
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),\r
+ kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),\r
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),\r
+ kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),\r
+ kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),\r
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),\r
+ kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),\r
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),\r
+ kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),\r
+ kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),\r
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),\r
+ kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),\r
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),\r
+ kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),\r
+ kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),\r
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),\r
+ kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),\r
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),\r
+ kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),\r
+ kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),\r
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),\r
+ kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),\r
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),\r
+ kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),\r
+ kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),\r
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),\r
+ kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),\r
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),\r
+\r
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),\r
+ kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),\r
+ kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),\r
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),\r
+ kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),\r
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),\r
+\r
+ kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),\r
+ kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),\r
+ kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),\r
+ kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),\r
+ kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),\r
+\r
+ kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),\r
+ kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),\r
+ kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2),\r
+ kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),\r
+\r
+ kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),\r
+ kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),\r
+ kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2),\r
+ kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),\r
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),\r
+ kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),\r
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),\r
+ kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),\r
+ kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),\r
+ kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),\r
+ kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),\r
+ kNONE_to_NONE = (int)0x80000000U,\r
+} clock_attach_id_t;\r
+\r
+/* Clock dividers */\r
+typedef enum _clock_div_name\r
+{\r
+ kCLOCK_DivSystickClk = 0,\r
+ kCLOCK_DivTraceClk = 1,\r
+ kCLOCK_DivAhbClk = 32,\r
+ kCLOCK_DivClkOut = 33,\r
+ kCLOCK_DivAdcAsyncClk = 37,\r
+ kCLOCK_DivUsbClk = 38,\r
+ kCLOCK_DivFrg = 40,\r
+ kCLOCK_DivFxI2s0MClk = 43\r
+} clock_div_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ if (index < 2)\r
+ {\r
+ SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+ else\r
+ {\r
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+}\r
+\r
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ if (index < 2)\r
+ {\r
+ SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+ else\r
+ {\r
+ ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ }\r
+}\r
+/**\r
+ * @brief FLASH Access time definitions\r
+ */\r
+typedef enum _clock_flashtim\r
+{\r
+ kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */\r
+ kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */\r
+ kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */\r
+ kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */\r
+ kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */\r
+ kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */\r
+} clock_flashtim_t;\r
+\r
+/**\r
+ * @brief Set FLASH memory access time in clocks\r
+ * @param clks : Clock cycles for FLASH access\r
+ * @return Nothing\r
+ */\r
+static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)\r
+{\r
+ uint32_t tmp;\r
+\r
+ tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);\r
+\r
+ /* Don't alter lower bits */\r
+ SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);\r
+}\r
+\r
+/**\r
+ * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).\r
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is\r
+ * enabled.\r
+ * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)\r
+ * @return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupFROClocking(uint32_t iFreq);\r
+/**\r
+ * @brief Configure the clock selection muxes.\r
+ * @param connection : Clock to be configured.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_AttachClk(clock_attach_id_t connection);\r
+/**\r
+ * @brief Get the actual clock attach id.\r
+ * This fuction uses the offset in input attach id, then it reads the actual source value in\r
+ * the register and combine the offset to obtain an actual attach id.\r
+ * @param attachId : Clock attach id to get.\r
+ * @return Clock source value.\r
+ */\r
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);\r
+/**\r
+ * @brief Setup peripheral clock dividers.\r
+ * @param div_name : Clock divider name\r
+ * @param divided_by_value: Value to be divided\r
+ * @param reset : Whether to reset the divider counter.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);\r
+/**\r
+ * @brief Set the flash wait states for the input freuqency.\r
+ * @param iFreq : Input frequency\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);\r
+/*! @brief Return Frequency of selected clock\r
+ * @return Frequency of selected clock\r
+ */\r
+uint32_t CLOCK_GetFreq(clock_name_t clockName);\r
+\r
+/*! @brief Return Input frequency for the Fractional baud rate generator\r
+ * @return Input Frequency for FRG\r
+ */\r
+uint32_t CLOCK_GetFRGInputClock(void);\r
+\r
+/*! @brief Set output of the Fractional baud rate generator\r
+ * @param freq : Desired output frequency\r
+ * @return Error Code 0 - fail 1 - success\r
+ */\r
+uint32_t CLOCK_SetFRGClock(uint32_t freq);\r
+\r
+/*! @brief Return Frequency of FRO 12MHz\r
+ * @return Frequency of FRO 12MHz\r
+ */\r
+uint32_t CLOCK_GetFro12MFreq(void);\r
+/*! @brief Return Frequency of External Clock\r
+ * @return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+uint32_t CLOCK_GetExtClkFreq(void);\r
+/*! @brief Return Frequency of Watchdog Oscillator\r
+ * @return Frequency of Watchdog Oscillator\r
+ */\r
+uint32_t CLOCK_GetWdtOscFreq(void);\r
+/*! @brief Return Frequency of High-Freq output of FRO\r
+ * @return Frequency of High-Freq output of FRO\r
+ */\r
+uint32_t CLOCK_GetFroHfFreq(void);\r
+/*! @brief Return Frequency of PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPllOutFreq(void);\r
+/*! @brief Return Frequency of 32kHz osc\r
+ * @return Frequency of 32kHz osc\r
+ */\r
+uint32_t CLOCK_GetOsc32KFreq(void);\r
+/*! @brief Return Frequency of Core System\r
+ * @return Frequency of Core System\r
+ */\r
+uint32_t CLOCK_GetCoreSysClkFreq(void);\r
+/*! @brief Return Frequency of I2S MCLK Clock\r
+ * @return Frequency of I2S MCLK Clock\r
+ */\r
+uint32_t CLOCK_GetI2SMClkFreq(void);\r
+/*! @brief Return Frequency of Flexcomm functional Clock\r
+ * @return Frequency of Flexcomm functional Clock\r
+ */\r
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);\r
+/*! @brief Return Frequency of Adc Clock\r
+ * @return Frequency of Adc Clock.\r
+ */\r
+uint32_t CLOCK_GetAdcClkFreq(void);\r
+/*! @brief Return Asynchronous APB Clock source\r
+ * @return Asynchronous APB CLock source\r
+ */\r
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)\r
+{\r
+ return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);\r
+}\r
+/*! @brief Return Frequency of Asynchronous APB Clock\r
+ * @return Frequency of Asynchronous APB Clock Clock\r
+ */\r
+uint32_t CLOCK_GetAsyncApbClkFreq(void);\r
+/*! @brief Return System PLL input clock rate\r
+ * @return System PLL input clock rate\r
+ */\r
+uint32_t CLOCK_GetSystemPLLInClockRate(void);\r
+\r
+/*! @brief Return System PLL output clock rate\r
+ * @param recompute : Forces a PLL rate recomputation if true\r
+ * @return System PLL output clock rate\r
+ * @note The PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);\r
+\r
+/*! @brief Enables and disables PLL bypass mode\r
+ * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass\r
+ * @return System PLL output clock rate\r
+ */\r
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)\r
+{\r
+ if (bypass)\r
+ {\r
+ SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);\r
+ }\r
+}\r
+\r
+/*! @brief Check if PLL is locked or not\r
+ * @return true if the PLL is locked, false if not locked\r
+ */\r
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)\r
+{\r
+ return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);\r
+}\r
+\r
+/*! @brief Store the current PLL rate\r
+ * @param rate: Current rate of the PLL\r
+ * @return Nothing\r
+ **/\r
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);\r
+\r
+/*! @brief PLL configuration structure flags for 'flags' field\r
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the\r
+ * configuration structure must be assigned with the expected PLL frequency. If the\r
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration\r
+ * function and the driver will determine the PLL rate from the currently selected\r
+ * PLL source. This flag might be used to configure the PLL input clock more accurately\r
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the\r
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider\r
+ * are not used.<br>\r
+ */\r
+#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */\r
+#define PLL_CONFIGFLAG_FORCENOFRACT \\r
+ (1 \\r
+ << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \\r
+ \ \ \ \\r
+ \ \ \ \ \ \\r
+ \ \ \ \ \ \ \ \\r
+ \ \ \ \ \ \ \ \ \ \\r
+ \ \ \ \ \ \ \ \ \ \ \ \\r
+ hardware */\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency\r
+ * See (MF) field in the SYSPLLSSCTRL1 register in the UM.\r
+ */\r
+typedef enum _ss_progmodfm\r
+{\r
+ kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */\r
+ kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */\r
+ kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */\r
+ kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */\r
+ kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */\r
+ kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */\r
+ kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */\r
+ kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */\r
+} ss_progmodfm_t;\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth\r
+ * See (MR) field in the SYSPLLSSCTRL1 register in the UM.\r
+ */\r
+typedef enum _ss_progmoddp\r
+{\r
+ kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */\r
+ kSS_MR_K1 = (1 << 23), /*!< k = 1 */\r
+ kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */\r
+ kSS_MR_K2 = (3 << 23), /*!< k = 2 */\r
+ kSS_MR_K3 = (4 << 23), /*!< k = 3 */\r
+ kSS_MR_K4 = (5 << 23), /*!< k = 4 */\r
+ kSS_MR_K6 = (6 << 23), /*!< k = 6 */\r
+ kSS_MR_K8 = (7 << 23) /*!< k = 8 */\r
+} ss_progmoddp_t;\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Modulation waveform control\r
+ * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>\r
+ * Compensation for low pass filtering of the PLL to get a triangular\r
+ * modulation at the output of the PLL, giving a flat frequency spectrum.\r
+ */\r
+typedef enum _ss_modwvctrl\r
+{\r
+ kSS_MC_NOC = (0 << 26), /*!< no compensation */\r
+ kSS_MC_RECC = (2 << 26), /*!< recommended setting */\r
+ kSS_MC_MAXC = (3 << 26), /*!< max. compensation */\r
+} ss_modwvctrl_t;\r
+\r
+/*! @brief PLL configuration structure\r
+ *\r
+ * This structure can be used to configure the settings for a PLL\r
+ * setup structure. Fill in the desired configuration for the PLL\r
+ * and call the PLL setup function to fill in a PLL setup structure.\r
+ */\r
+typedef struct _pll_config\r
+{\r
+ uint32_t desiredRate; /*!< Desired PLL rate in Hz */\r
+ uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */\r
+ uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */\r
+ ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ ss_modwvctrl_t\r
+ ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+\r
+} pll_config_t;\r
+\r
+/*! @brief PLL setup structure flags for 'flags' field\r
+ * These flags control how the PLL setup function sets up the PLL\r
+ */\r
+#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */\r
+#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */\r
+#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */\r
+#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */\r
+\r
+/*! @brief PLL setup structure\r
+ * This structure can be used to pre-build a PLL setup configuration\r
+ * at run-time and quickly set the PLL to the configuration. It can be\r
+ * populated with the PLL setup function. If powering up or waiting\r
+ * for PLL lock, the PLL input clock source should be configured prior\r
+ * to PLL setup.\r
+ */\r
+typedef struct _pll_setup\r
+{\r
+ uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */\r
+ uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */\r
+ uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */\r
+ uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */\r
+ uint32_t pllRate; /*!< Acutal PLL rate */\r
+ uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */\r
+} pll_setup_t;\r
+\r
+/*! @brief PLL status definitions\r
+ */\r
+typedef enum _pll_error\r
+{\r
+ kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */\r
+ kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */\r
+ kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */\r
+ kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */\r
+ kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */\r
+ kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */\r
+} pll_error_t;\r
+\r
+/*! @brief USB clock source definition. */\r
+typedef enum _clock_usb_src\r
+{\r
+ kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */\r
+ kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */\r
+ kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */\r
+ kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(\r
+ 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */\r
+} clock_usb_src_t;\r
+\r
+/*! @brief Return System PLL output clock rate from setup structure\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate calculated from the setup structure\r
+ */\r
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output based on the passed PLL setup data\r
+ * @param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * @param pSetup : Pointer to PLL setup structure to be filled\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @param flagcfg : Flag configuration for PLL config structure\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);\r
+\r
+/**\r
+ * @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output based on the multiplier and input frequency\r
+ * @param multiply_by : multiplier\r
+ * @param input_freq : Clock input frequency of the PLL\r
+ * @return Nothing\r
+ * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+ * function does not disable or enable PLL power, wait for PLL lock,\r
+ * or adjust system voltages. These must be done in the application.\r
+ * The function will not alter any source clocks (ie, main systen clock)\r
+ * that may use the PLL, so these should be setup prior to and after\r
+ * exiting the function.\r
+ */\r
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);\r
+\r
+/*! @brief Disable USB FS clock.\r
+ *\r
+ * Disable USB FS clock.\r
+ */\r
+static inline void CLOCK_DisableUsbfs0Clock(void)\r
+{\r
+ CLOCK_DisableClock(kCLOCK_Usbd0);\r
+}\r
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);\r
+\r
+/*!\r
+ * @brief Use DWT to delay at least for some time.\r
+ * Please note that, this API will calculate the microsecond period with the maximum devices\r
+ * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise\r
+ * delay count was needed, please implement a new timer count to achieve this function.\r
+ *\r
+ * @param delay_us Delay time in unit of microsecond.\r
+ */\r
+void SDK_DelayAtLeastUs(uint32_t delay_us);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_CLOCK_H_ */\r
projects / freertos / blobdiff