+++ /dev/null
-/*\r
- * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
- * Copyright 2016-2017 NXP\r
- * All rights reserved.\r
- *\r
- * SPDX-License-Identifier: BSD-3-Clause\r
- */\r
-\r
-#include "fsl_pint.h"\r
-\r
-/* Component ID definition, used by tools. */\r
-#ifndef FSL_COMPONENT_ID\r
-#define FSL_COMPONENT_ID "platform.drivers.pint"\r
-#endif\r
-\r
-/*******************************************************************************\r
- * Variables\r
- ******************************************************************************/\r
-\r
-#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)\r
-/*! @brief Irq number array */\r
-static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS +\r
- FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;\r
-\r
-/*! @brief Callback function array for PINT(s). */\r
-static pint_cb_t\r
- s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS];\r
-#else\r
-/*! @brief Irq number array */\r
-static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;\r
-\r
-/*! @brief Callback function array for PINT(s). */\r
-static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];\r
-#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */\r
-\r
-/*******************************************************************************\r
- * Code\r
- ******************************************************************************/\r
-\r
-/*!\r
- * brief Initialize PINT peripheral.\r
-\r
- * This function initializes the PINT peripheral and enables the clock.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- *\r
- * retval None.\r
- */\r
-void PINT_Init(PINT_Type *base)\r
-{\r
- uint32_t i;\r
- uint32_t pmcfg;\r
- uint8_t pintcount;\r
- assert(base);\r
- pmcfg = 0;\r
-\r
-#if defined(SECPINT)\r
- pintcount = SEC_PINT_PIN_INT_COUNT;\r
-#else\r
- pintcount = PINT_PIN_INT_COUNT;\r
-#endif /* SECPINT */\r
-\r
- for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)\r
- {\r
- s_pintCallback[i] = NULL;\r
- }\r
-\r
- /* Disable all bit slices for pint*/\r
- for (i = 0; i < pintcount; i++)\r
- {\r
- pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));\r
- }\r
-\r
-#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_EnableClock(kCLOCK_GpioInt);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_EnableClock(kCLOCK_Gpio0);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if defined(SECPINT)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_EnableClock(kCLOCK_Gpio_Sec);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-#endif /* SECPINT */\r
-#else\r
- /* if need config SECURE PINT device,then enable secure pint interrupt clock */\r
- if (base == PINT)\r
- {\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_EnableClock(kCLOCK_Pint);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
- }\r
-#if defined(SECPINT)\r
- else if (base == SECPINT)\r
- {\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_EnableClock(kCLOCK_Gpio_sec_Int);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
- }\r
-#endif /* SECPINT */\r
-#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */\r
-\r
- /* Disable all pattern match bit slices */\r
- base->PMCFG = pmcfg;\r
-}\r
-\r
-/*!\r
- * brief Configure PINT peripheral pin interrupt.\r
-\r
- * This function configures a given pin interrupt.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- * param intr Pin interrupt.\r
- * param enable Selects detection logic.\r
- * param callback Callback.\r
- *\r
- * retval None.\r
- */\r
-void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)\r
-{\r
- assert(base);\r
-\r
- /* Clear Rise and Fall flags first */\r
- PINT_PinInterruptClrRiseFlag(base, intr);\r
- PINT_PinInterruptClrFallFlag(base, intr);\r
-\r
- /* select level or edge sensitive */\r
- base->ISEL =\r
- (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U);\r
-\r
- /* enable rising or level interrupt */\r
- if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))\r
- {\r
- base->SIENR = 1UL << (uint32_t)intr;\r
- }\r
- else\r
- {\r
- base->CIENR = 1UL << (uint32_t)intr;\r
- }\r
-\r
- /* Enable falling or select high level */\r
- if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)\r
- {\r
- base->SIENF = 1UL << (uint32_t)intr;\r
- }\r
- else\r
- {\r
- base->CIENF = 1UL << (uint32_t)intr;\r
- }\r
-\r
- s_pintCallback[intr] = callback;\r
-}\r
-\r
-/*!\r
- * brief Get PINT peripheral pin interrupt configuration.\r
-\r
- * This function returns the configuration of a given pin interrupt.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- * param pintr Pin interrupt.\r
- * param enable Pointer to store the detection logic.\r
- * param callback Callback.\r
- *\r
- * retval None.\r
- */\r
-void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)\r
-{\r
- uint32_t mask;\r
- bool level;\r
-\r
- assert(base);\r
-\r
- *enable = kPINT_PinIntEnableNone;\r
- level = false;\r
-\r
- mask = 1UL << (uint32_t)pintr;\r
- if ((base->ISEL & mask) != 0U)\r
- {\r
- /* Pin interrupt is level sensitive */\r
- level = true;\r
- }\r
-\r
- if ((base->IENR & mask) != 0U)\r
- {\r
- if (level)\r
- {\r
- /* Level interrupt is enabled */\r
- *enable = kPINT_PinIntEnableLowLevel;\r
- }\r
- else\r
- {\r
- /* Rising edge interrupt */\r
- *enable = kPINT_PinIntEnableRiseEdge;\r
- }\r
- }\r
-\r
- if ((base->IENF & mask) != 0U)\r
- {\r
- if (level)\r
- {\r
- /* Level interrupt is active high */\r
- *enable = kPINT_PinIntEnableHighLevel;\r
- }\r
- else\r
- {\r
- /* Either falling or both edge */\r
- if (*enable == kPINT_PinIntEnableRiseEdge)\r
- {\r
- /* Rising and faling edge */\r
- *enable = kPINT_PinIntEnableBothEdges;\r
- }\r
- else\r
- {\r
- /* Falling edge */\r
- *enable = kPINT_PinIntEnableFallEdge;\r
- }\r
- }\r
- }\r
-\r
- *callback = s_pintCallback[pintr];\r
-}\r
-\r
-/*!\r
- * brief Configure PINT pattern match.\r
-\r
- * This function configures a given pattern match bit slice.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- * param bslice Pattern match bit slice number.\r
- * param cfg Pointer to bit slice configuration.\r
- *\r
- * retval None.\r
- */\r
-void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)\r
-{\r
- uint32_t src_shift;\r
- uint32_t cfg_shift;\r
- uint32_t pmcfg;\r
- uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;\r
- uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;\r
-\r
- assert(base);\r
-\r
- src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);\r
- cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);\r
-\r
- /* Input source selection for selected bit slice */\r
- base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift);\r
-\r
- /* Bit slice configuration */\r
- pmcfg = base->PMCFG;\r
- pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift);\r
-\r
- /* If end point is true, enable the bits */\r
- if ((uint32_t)bslice != 7UL)\r
- {\r
- if (cfg->end_point)\r
- {\r
- pmcfg |= (1UL << (uint32_t)bslice);\r
- }\r
- else\r
- {\r
- pmcfg &= ~(1UL << (uint32_t)bslice);\r
- }\r
- }\r
-\r
- base->PMCFG = pmcfg;\r
-\r
- /* Save callback pointer */\r
- s_pintCallback[bslice] = cfg->callback;\r
-}\r
-\r
-/*!\r
- * brief Get PINT pattern match configuration.\r
-\r
- * This function returns the configuration of a given pattern match bit slice.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- * param bslice Pattern match bit slice number.\r
- * param cfg Pointer to bit slice configuration.\r
- *\r
- * retval None.\r
- */\r
-void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)\r
-{\r
- uint32_t src_shift;\r
- uint32_t cfg_shift;\r
- uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;\r
- uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;\r
-\r
- assert(base);\r
-\r
- src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);\r
- cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);\r
-\r
- cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift);\r
- cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift);\r
-\r
- if ((uint32_t)bslice == 7U)\r
- {\r
- cfg->end_point = true;\r
- }\r
- else\r
- {\r
- cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice);\r
- }\r
- cfg->callback = s_pintCallback[bslice];\r
-}\r
-\r
-/*!\r
- * brief Reset pattern match detection logic.\r
-\r
- * This function resets the pattern match detection logic if any of the product term is matching.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- *\r
- * retval pmstatus Each bit position indicates the match status of corresponding bit slice.\r
- * = 0 Match was detected. = 1 Match was not detected.\r
- */\r
-uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)\r
-{\r
- uint32_t pmctrl;\r
- uint32_t pmstatus;\r
- uint32_t pmsrc;\r
-\r
- pmctrl = base->PMCTRL;\r
- pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;\r
- if (pmstatus != 0UL)\r
- {\r
- /* Reset Pattern match engine detection logic */\r
- pmsrc = base->PMSRC;\r
- base->PMSRC = pmsrc;\r
- }\r
- return (pmstatus);\r
-}\r
-\r
-/*!\r
- * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive.\r
-\r
- * This function clears the selected pin interrupt status.\r
- *\r
- * @param base Base address of the PINT peripheral.\r
- * @param pintr Pin interrupt.\r
- *\r
- * @retval None.\r
- */\r
-void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)\r
-{\r
- uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr);\r
- uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr);\r
-\r
- /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */\r
- if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))\r
- {\r
- base->IST = (1UL << (uint32_t)pintr);\r
- }\r
-}\r
-\r
-/*!\r
- * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive.\r
-\r
- * This function clears the status of all pin interrupts.\r
- *\r
- * @param base Base address of the PINT peripheral.\r
- *\r
- * @retval None.\r
- */\r
-void PINT_PinInterruptClrStatusAll(PINT_Type *base)\r
-{\r
- uint32_t pinIntMode = 0;\r
- uint32_t pinIntStatus = 0;\r
- uint32_t mask = 0;\r
- uint32_t i;\r
-\r
- for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)\r
- {\r
- pinIntMode = base->ISEL & (1UL << i);\r
- pinIntStatus = base->IST & (1UL << i);\r
-\r
- /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */\r
- if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))\r
- {\r
- mask |= 1UL << i;\r
- }\r
- }\r
-\r
- base->IST = mask;\r
-}\r
-\r
-/*!\r
- * brief Enable callback.\r
-\r
- * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored\r
- * as soon as they are enabled, the callback function is not enabled until this function is called.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- *\r
- * retval None.\r
- */\r
-void PINT_EnableCallback(PINT_Type *base)\r
-{\r
- uint32_t i;\r
-\r
- assert(base);\r
-\r
- for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)\r
- {\r
- NVIC_ClearPendingIRQ(s_pintIRQ[i]);\r
- PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);\r
- (void)EnableIRQ(s_pintIRQ[i]);\r
- }\r
-}\r
-\r
-/*!\r
- * brief enable callback by pin index.\r
-\r
- * This function enables callback by pin index instead of enabling all pins.\r
- *\r
- * param base Base address of the peripheral.\r
- * param pinIdx pin index.\r
- *\r
- * retval None.\r
- */\r
-void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)\r
-{\r
- assert(base);\r
-\r
- NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);\r
- PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);\r
- (void)EnableIRQ(s_pintIRQ[pintIdx]);\r
-}\r
-\r
-/*!\r
- * brief Disable callback.\r
-\r
- * This function disables the interrupt for the selected PINT peripheral. Although the pins are still\r
- * being monitored but the callback function is not called.\r
- *\r
- * param base Base address of the peripheral.\r
- *\r
- * retval None.\r
- */\r
-void PINT_DisableCallback(PINT_Type *base)\r
-{\r
- uint32_t i;\r
-\r
- assert(base);\r
-\r
- for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)\r
- {\r
- (void)DisableIRQ(s_pintIRQ[i]);\r
- PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);\r
- NVIC_ClearPendingIRQ(s_pintIRQ[i]);\r
- }\r
-}\r
-\r
-/*!\r
- * brief disable callback by pin index.\r
-\r
- * This function disables callback by pin index instead of disabling all pins.\r
- *\r
- * param base Base address of the peripheral.\r
- * param pinIdx pin index.\r
- *\r
- * retval None.\r
- */\r
-void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)\r
-{\r
- assert(base);\r
-\r
- (void)DisableIRQ(s_pintIRQ[pintIdx]);\r
- PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);\r
- NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);\r
-}\r
-\r
-/*!\r
- * brief Deinitialize PINT peripheral.\r
-\r
- * This function disables the PINT clock.\r
- *\r
- * param base Base address of the PINT peripheral.\r
- *\r
- * retval None.\r
- */\r
-void PINT_Deinit(PINT_Type *base)\r
-{\r
- uint32_t i;\r
-\r
- assert(base);\r
-\r
- /* Cleanup */\r
- PINT_DisableCallback(base);\r
- for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)\r
- {\r
- s_pintCallback[i] = NULL;\r
- }\r
-\r
-#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Disable the clock. */\r
- CLOCK_DisableClock(kCLOCK_GpioInt);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Disable the clock. */\r
- CLOCK_DisableClock(kCLOCK_Gpio0);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-\r
-#if defined(SECPINT)\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Enable the clock. */\r
- CLOCK_DisableClock(kCLOCK_Gpio_Sec);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-#endif /* SECPINT */\r
-#else\r
- if (base == PINT)\r
- {\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Disable the clock. */\r
- CLOCK_DisableClock(kCLOCK_Pint);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
- }\r
-#if defined(SECPINT)\r
- else if (base == SECPINT)\r
- {\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)\r
- /* Reset the module. */\r
- RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */\r
-\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* Disable the clock. */\r
- CLOCK_DisableClock(kCLOCK_Gpio_sec_Int);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
- }\r
-#endif /* SECPINT */\r
-#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */\r
-}\r
-#if defined(SECPINT)\r
-/* IRQ handler functions overloading weak symbols in the startup */\r
-void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus = 0;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_SecPinInt0] != NULL)\r
- {\r
- s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);\r
- }\r
- if ((SECPINT->ISEL & 0x1U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-\r
-#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)\r
-/* IRQ handler functions overloading weak symbols in the startup */\r
-void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_SecPinInt1] != NULL)\r
- {\r
- s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);\r
- }\r
- if ((SECPINT->ISEL & 0x1U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */\r
-#endif /* SECPINT */\r
-\r
-/* IRQ handler functions overloading weak symbols in the startup */\r
-void PIN_INT0_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt0] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x1U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)\r
-void PIN_INT1_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt1] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x2U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)\r
-void PIN_INT2_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt2] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x4U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)\r
-void PIN_INT3_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt3] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x8U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)\r
-void PIN_INT4_DriverIRQHandler(void)\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt4] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x10U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)\r
-#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER\r
-void PIN_INT5_DAC1_IRQHandler(void)\r
-#else\r
-void PIN_INT5_DriverIRQHandler(void)\r
-#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt5] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x20U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)\r
-#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER\r
-void PIN_INT6_USART3_IRQHandler(void)\r
-#else\r
-void PIN_INT6_DriverIRQHandler(void)\r
-#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt6] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x40U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
-\r
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)\r
-#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER\r
-void PIN_INT7_USART4_IRQHandler(void)\r
-#else\r
-void PIN_INT7_DriverIRQHandler(void)\r
-#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */\r
-{\r
- uint32_t pmstatus;\r
-\r
- /* Reset pattern match detection */\r
- pmstatus = PINT_PatternMatchResetDetectLogic(PINT);\r
- /* Call user function */\r
- if (s_pintCallback[kPINT_PinInt7] != NULL)\r
- {\r
- s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);\r
- }\r
- if ((PINT->ISEL & 0x80U) == 0x0U)\r
- {\r
- /* Edge sensitive: clear Pin interrupt after callback */\r
- PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);\r
- }\r
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
- exception return operation might vector to incorrect interrupt */\r
-#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
- __DSB();\r
-#endif\r
-}\r
-#endif\r
projects / freertos / blobdiff