--- /dev/null
+;/*\r
+;******************************************************************************\r
+;* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+;* You may use this software and any derivatives exclusively with\r
+;* Microchip products.\r
+;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+;* OF THESE TERMS.\r
+;******************************************************************************\r
+; */\r
+;/** @file startup_MEC1322.s\r
+; *MEC1322 API Test: startup and vector table\r
+; */\r
+;/** @defgroup startup_MEC1322\r
+; * @{\r
+; */\r
+\r
+ IMPORT __main\r
+ IMPORT |Image$$RW_IRAM1$$Base|\r
+ IMPORT |Image$$RW_IRAM1$$Limit|\r
+ IMPORT |Image$$RW_IRAM1$$Length|\r
+ IMPORT |Image$$RW_IRAM1$$ZI$$Base|\r
+ IMPORT |Image$$RW_IRAM1$$ZI$$Limit|\r
+ IMPORT |Image$$ER_IROM1$$Base|\r
+ IMPORT |Image$$ER_IROM1$$Limit|\r
+ IMPORT main\r
+ IMPORT system_set_ec_clock\r
+\r
+ EXPORT Reset_Handler\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000800\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+ EXPORT __stack_bottom\r
+__stack_bottom\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000 \r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __tx_vectors\r
+__tx_vectors\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; MEC1322 External Interrupts\r
+ DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0\r
+ DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1\r
+ DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2\r
+ DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3\r
+ DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0\r
+ DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1\r
+ DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2\r
+ DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3\r
+ DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4\r
+ DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5\r
+ DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6\r
+ DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7\r
+ DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error\r
+ DCD NVIC_Handler_UART0 ; 74h: 13, UART0\r
+ DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0\r
+ DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL\r
+ DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN\r
+ DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS\r
+ DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF\r
+ DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF\r
+ DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox\r
+ DCD NVIC_Handler_PECI ; A4h: 25, PECI\r
+ DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0\r
+ DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1\r
+ DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL\r
+ DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT\r
+ DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0\r
+ DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1\r
+ DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0\r
+ DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1\r
+ DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2\r
+ DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3\r
+ DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX\r
+ DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX\r
+ DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR\r
+ DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT\r
+ DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE\r
+ DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL\r
+ DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN\r
+ DCD NVIC_Handler_VBAT ; ECh: 43, VBAT\r
+ DCD NVIC_Handler_LED0 ; F0h: 44, LED0\r
+ DCD NVIC_Handler_LED1 ; F4h: 45, LED1\r
+ DCD NVIC_Handler_LED2 ; F8h: 46, LED2\r
+ DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR\r
+ DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY\r
+ DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0\r
+ DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1\r
+ DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2\r
+ DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3\r
+ DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4\r
+ DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5\r
+ DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX\r
+ DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX\r
+ DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08\r
+ DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09\r
+ DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10\r
+ DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11\r
+ DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12\r
+ DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13\r
+ DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14\r
+ DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15\r
+ DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16\r
+ DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17\r
+ DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18\r
+ DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19\r
+ DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20\r
+ DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21\r
+ DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22\r
+ DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23\r
+ DCD NVIC_Handler_073 ; 164h: 73, unknown\r
+ DCD NVIC_Handler_074 ; 168h: 74, unknown\r
+ DCD NVIC_Handler_075 ; 16Ch: 75, unknown\r
+ DCD NVIC_Handler_076 ; 170h: 76, unknown\r
+ DCD NVIC_Handler_077 ; 174h: 77, unknown\r
+ DCD NVIC_Handler_078 ; 178h: 78, unknown\r
+ DCD NVIC_Handler_079 ; 17Ch: 79, unknown\r
+ DCD NVIC_Handler_080 ; 180h: 80, unknown\r
+ DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8\r
+ DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9\r
+ DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10\r
+ DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11\r
+ DCD NVIC_Handler_LED3 ; 194h: 85, LED3\r
+ DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error\r
+ DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End\r
+ DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen\r
+ DCD NVIC_Handler_AES ; 1A4h: 89, AES \r
+ DCD NVIC_Handler_HASH ; 1A8h: 90, HASH\r
+ \r
+\r
+ AREA ROMTABLE, CODE, READONLY\r
+ THUMB\r
+; ---------- ROM API ----------\r
+; Jump table to ROM API C functions\r
+;\r
+;\r
+; ---------- ROM API End ------\r
+; Reset Handler\r
+\r
+ AREA |.text|, CODE, READONLY\r
+ THUMB\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+\r
+ CPSID i\r
+ \r
+ ; support code is loaded from ROM loader\r
+ LDR SP, =__initial_sp\r
+ ; configure CPU speed \r
+ LDR R0, =system_set_ec_clock\r
+ BLX R0\r
+\r
+ LDR SP, =__initial_sp\r
+\r
+ ; support FPU\r
+ IF {CPU} = "Cortex-M4.fp"\r
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
+ LDR R1,[R0]\r
+ ORR R1,R1,#(0xF << 20)\r
+ STR R1,[R0]\r
+ ENDIF\r
+\r
+ ; Enter Keil startup code which calls our main\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ MOV R7,#1\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ MOV R7,#2\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ MOV R7,#3\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ MOV R7,#4\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ MOV R7,#5\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ MOV R7,#6\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ MOV R7,#7\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ MOV R7,#8\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ MOV R7,#9\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ ; External MEC1322 NVIC Interrupt Inputs\r
+ EXPORT NVIC_Handler_I2C0 [WEAK]\r
+ EXPORT NVIC_Handler_I2C1 [WEAK]\r
+ EXPORT NVIC_Handler_I2C2 [WEAK]\r
+ EXPORT NVIC_Handler_I2C3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA0 [WEAK]\r
+ EXPORT NVIC_Handler_DMA1 [WEAK]\r
+ EXPORT NVIC_Handler_DMA2 [WEAK]\r
+ EXPORT NVIC_Handler_DMA3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA4 [WEAK]\r
+ EXPORT NVIC_Handler_DMA5 [WEAK]\r
+ EXPORT NVIC_Handler_DMA6 [WEAK]\r
+ EXPORT NVIC_Handler_DMA7 [WEAK]\r
+ EXPORT NVIC_Handler_LPCBERR [WEAK]\r
+ EXPORT NVIC_Handler_UART0 [WEAK]\r
+ EXPORT NVIC_Handler_IMAP0 [WEAK]\r
+ EXPORT NVIC_Handler_EC0_IBF [WEAK]\r
+ EXPORT NVIC_Handler_EC0_OBF [WEAK]\r
+ EXPORT NVIC_Handler_EC1_IBF [WEAK]\r
+ EXPORT NVIC_Handler_EC1_OBF [WEAK]\r
+ EXPORT NVIC_Handler_PM1_CTL [WEAK]\r
+ EXPORT NVIC_Handler_PM1_EN [WEAK]\r
+ EXPORT NVIC_Handler_PM1_STS [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_OBF [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_IBF [WEAK]\r
+ EXPORT NVIC_Handler_MAILBOX [WEAK]\r
+ EXPORT NVIC_Handler_PECI [WEAK]\r
+ EXPORT NVIC_Handler_TACH0 [WEAK]\r
+ EXPORT NVIC_Handler_TACH1 [WEAK]\r
+ EXPORT NVIC_Handler_ADC_SNGL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_RPT [WEAK]\r
+ EXPORT NVIC_Handler_V2P_INT0 [WEAK]\r
+ EXPORT NVIC_Handler_V2P_INT1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH0 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH2 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH3 [WEAK]\r
+ EXPORT NVIC_Handler_SPI0_TX [WEAK]\r
+ EXPORT NVIC_Handler_SPI0_RX [WEAK]\r
+ EXPORT NVIC_Handler_HIB_TMR [WEAK]\r
+ EXPORT NVIC_Handler_KEY_INT [WEAK]\r
+ EXPORT NVIC_Handler_KEY_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_RPM_STALL [WEAK]\r
+ EXPORT NVIC_Handler_RPM_SPIN [WEAK]\r
+ EXPORT NVIC_Handler_VBAT [WEAK]\r
+ EXPORT NVIC_Handler_LED0 [WEAK]\r
+ EXPORT NVIC_Handler_LED1 [WEAK]\r
+ EXPORT NVIC_Handler_LED2 [WEAK]\r
+ EXPORT NVIC_Handler_MBC_ERR [WEAK]\r
+ EXPORT NVIC_Handler_MBC_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_TMR0 [WEAK]\r
+ EXPORT NVIC_Handler_TMR1 [WEAK]\r
+ EXPORT NVIC_Handler_TMR2 [WEAK]\r
+ EXPORT NVIC_Handler_TMR3 [WEAK]\r
+ EXPORT NVIC_Handler_TMR4 [WEAK]\r
+ EXPORT NVIC_Handler_TMR5 [WEAK]\r
+ EXPORT NVIC_Handler_SPI1_TX [WEAK]\r
+ EXPORT NVIC_Handler_SPI1_RX [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ08 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ09 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ10 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ11 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ12 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ13 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ14 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ15 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ16 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ17 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ18 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ19 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ20 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ21 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ22 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ23 [WEAK]\r
+ EXPORT NVIC_Handler_073 [WEAK]\r
+ EXPORT NVIC_Handler_074 [WEAK]\r
+ EXPORT NVIC_Handler_075 [WEAK]\r
+ EXPORT NVIC_Handler_076 [WEAK]\r
+ EXPORT NVIC_Handler_077 [WEAK]\r
+ EXPORT NVIC_Handler_078 [WEAK]\r
+ EXPORT NVIC_Handler_079 [WEAK]\r
+ EXPORT NVIC_Handler_080 [WEAK]\r
+ EXPORT NVIC_Handler_DMA8 [WEAK]\r
+ EXPORT NVIC_Handler_DMA9 [WEAK]\r
+ EXPORT NVIC_Handler_DMA10 [WEAK]\r
+ EXPORT NVIC_Handler_DMA11 [WEAK]\r
+ EXPORT NVIC_Handler_LED3 [WEAK]\r
+ EXPORT NVIC_Handler_PKE_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PKE_END [WEAK]\r
+ EXPORT NVIC_Handler_TRNG [WEAK]\r
+ EXPORT NVIC_Handler_AES [WEAK]\r
+ EXPORT NVIC_Handler_HASH [WEAK]\r
+\r
+NVIC_Handler_I2C0\r
+NVIC_Handler_I2C1\r
+NVIC_Handler_I2C2\r
+NVIC_Handler_I2C3\r
+NVIC_Handler_DMA0\r
+NVIC_Handler_DMA1\r
+NVIC_Handler_DMA2\r
+NVIC_Handler_DMA3\r
+NVIC_Handler_DMA4\r
+NVIC_Handler_DMA5\r
+NVIC_Handler_DMA6\r
+NVIC_Handler_DMA7\r
+NVIC_Handler_LPCBERR\r
+NVIC_Handler_UART0\r
+NVIC_Handler_IMAP0\r
+NVIC_Handler_EC0_IBF\r
+NVIC_Handler_EC0_OBF\r
+NVIC_Handler_EC1_IBF\r
+NVIC_Handler_EC1_OBF\r
+NVIC_Handler_PM1_CTL\r
+NVIC_Handler_PM1_EN\r
+NVIC_Handler_PM1_STS\r
+NVIC_Handler_MIF8042_OBF\r
+NVIC_Handler_MIF8042_IBF\r
+NVIC_Handler_MAILBOX\r
+NVIC_Handler_PECI\r
+NVIC_Handler_TACH0\r
+NVIC_Handler_TACH1\r
+NVIC_Handler_ADC_SNGL\r
+NVIC_Handler_ADC_RPT\r
+NVIC_Handler_V2P_INT0\r
+NVIC_Handler_V2P_INT1\r
+NVIC_Handler_PS2_CH0\r
+NVIC_Handler_PS2_CH1\r
+NVIC_Handler_PS2_CH2\r
+NVIC_Handler_PS2_CH3\r
+NVIC_Handler_SPI0_TX\r
+NVIC_Handler_SPI0_RX\r
+NVIC_Handler_HIB_TMR\r
+NVIC_Handler_KEY_INT\r
+NVIC_Handler_KEY_WAKE\r
+NVIC_Handler_RPM_STALL\r
+NVIC_Handler_RPM_SPIN\r
+NVIC_Handler_VBAT\r
+NVIC_Handler_LED0\r
+NVIC_Handler_LED1\r
+NVIC_Handler_LED2\r
+NVIC_Handler_MBC_ERR\r
+NVIC_Handler_MBC_BUSY\r
+NVIC_Handler_TMR0\r
+NVIC_Handler_TMR1\r
+NVIC_Handler_TMR2\r
+NVIC_Handler_TMR3\r
+NVIC_Handler_TMR4\r
+NVIC_Handler_TMR5\r
+NVIC_Handler_SPI1_TX\r
+NVIC_Handler_SPI1_RX\r
+NVIC_Handler_GIRQ08\r
+NVIC_Handler_GIRQ09\r
+NVIC_Handler_GIRQ10\r
+NVIC_Handler_GIRQ11\r
+NVIC_Handler_GIRQ12\r
+NVIC_Handler_GIRQ13\r
+NVIC_Handler_GIRQ14\r
+NVIC_Handler_GIRQ15\r
+NVIC_Handler_GIRQ16\r
+NVIC_Handler_GIRQ17\r
+NVIC_Handler_GIRQ18\r
+NVIC_Handler_GIRQ19\r
+NVIC_Handler_GIRQ20\r
+NVIC_Handler_GIRQ21\r
+NVIC_Handler_GIRQ22\r
+NVIC_Handler_GIRQ23\r
+NVIC_Handler_073\r
+NVIC_Handler_074\r
+NVIC_Handler_075\r
+NVIC_Handler_076\r
+NVIC_Handler_077\r
+NVIC_Handler_078\r
+NVIC_Handler_079\r
+NVIC_Handler_080\r
+NVIC_Handler_DMA8\r
+NVIC_Handler_DMA9\r
+NVIC_Handler_DMA10\r
+NVIC_Handler_DMA11\r
+NVIC_Handler_LED3\r
+NVIC_Handler_PKE_ERR\r
+NVIC_Handler_PKE_END\r
+NVIC_Handler_TRNG\r
+NVIC_Handler_AES\r
+NVIC_Handler_HASH\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ EXPORT __stack_bottom\r
+\r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;/** @}\r
+; */\r
projects / freertos / blobdiff