\r
/* Hardware register locations. */\r
#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
-#define tmrMMCR_EC_INTERRUPT_CONTROL ( * ( volatile uint8_t * ) 0x4000FC18 )\r
\r
#define tmrRECORD_NESTING_DEPTH() \\r
ulNestingDepth++; \\r
const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
\r
tmrGIRQ23_ENABLE_SET = 0x03;\r
- tmrMMCR_EC_INTERRUPT_CONTROL = 1; \r
- \r
- /* Initialise the three timers as described at the top of this file, and \r
+\r
+ /* Initialise the three timers as described at the top of this file, and\r
enable their interrupts in the NVIC. */\r
btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
- btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 ); \r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );\r
enable_timer0_irq();\r
NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431\r
NVIC_ClearPendingIRQ( TIMER0_IRQn );\r