allowing an additional paths through the code to be tested. */\r
#define lpINCLUDE_TEST_TIMER 0\r
\r
-/* Some registers are accessed directly as the library is not compatible with\r
-all the compilers used. */\r
+/* Registers and bits required to use the htimer in aggregated mode. */\r
#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )\r
#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )\r
#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )\r
#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )\r
-#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )\r
+#define lpEC_GIRQ17_SOURCE ( * ( volatile uint32_t * ) 0x4000C0B4 )\r
+#define lpEC_GIRQ17_ENABLE_CLEAR ( * ( volatile uint32_t * ) 0x4000C0C0 )\r
+#define lpBLOCK_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000c200 )\r
+#define lpGIRQ17_BIT_HTIMER ( 1UL << 20UL )\r
+#define lpHTIMER_GIRQ_BLOCK ( 1Ul << 17UL )\r
+\r
+/* Registers and bits required to use btimer 0 in aggregated mode. */\r
+#define lpGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+#define lpEC_GIRQ23_SOURCE ( * ( volatile uint32_t * ) 0x4000C12C )\r
+#define lpEC_GIRQ23_ENABLE_CLEAR ( * ( volatile uint32_t * ) 0x4000C138 )\r
+#define lpGIRQ23_BIT_TIMER0 ( 1UL << 0UL )\r
+#define lpBTIMER_GIRQ_BLOCK ( 1UL << 23UL )\r
\r
/*\r
* The low power demo does not use the SysTick, so override the\r
\r
/*-----------------------------------------------------------*/\r
\r
-void NVIC_Handler_HIB_TMR( void )\r
+void NVIC_Handler_GIRQ17( void )\r
{\r
- lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
+ /* The low power demo is using aggregated interrupts, so although in the\r
+ demo the htimer is the only peripheral that will generate interrupts on\r
+ this vector, in a real application it would be necessary to first check the\r
+ interrupt source. */\r
+ if( ( lpEC_GIRQ17_SOURCE & lpGIRQ17_BIT_HTIMER ) != 0 )\r
+ {\r
+ /* The htimer interrupted. Clear the interrupt. */\r
+ lpEC_GIRQ17_SOURCE = lpGIRQ17_BIT_HTIMER;\r
+ lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulHighResolutionReloadValue;\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
+ /* The CPU woke because of a tick. */\r
+ ulTickFlag = pdTRUE;\r
+ }\r
+ else\r
{\r
- /* A context switch is required. Context switching is performed in\r
- the PendSV interrupt. Pend the PendSV interrupt. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ /* Don't expect any other interrupts to use this vector in this\r
+ demo. Force an assert. */\r
+ configASSERT( lpEC_GIRQ17_SOURCE == 0 );\r
}\r
-\r
- /* The CPU woke because of a tick. */\r
- ulTickFlag = pdTRUE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( lpINCLUDE_TEST_TIMER == 1 )\r
\r
- #define lpGIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )\r
- #define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )\r
-\r
static void prvSetupBasicTimer( void )\r
{\r
const uint8_t ucTimerChannel = 0;\r
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;\r
\r
- lpGIRQ23_ENABLE_SET = tmrGIRQ23_BIT_TIMER0;\r
+ /* Enable btimer 0 interrupt in the aggregated GIRQ23 block. */\r
+ lpEC_GIRQ23_SOURCE = lpGIRQ23_BIT_TIMER0;\r
+ lpEC_GIRQ23_ENABLE_CLEAR = lpGIRQ23_BIT_TIMER0;\r
+ lpBLOCK_ENABLE_SET = lpBTIMER_GIRQ_BLOCK;\r
+ lpGIRQ23_ENABLE_SET = lpGIRQ23_BIT_TIMER0;\r
\r
/* To fully test the low power tick processing it is necessary to sometimes\r
bring the MCU out of its sleep state by a method other than the tick\r
purpose. */\r
btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
btimer_interrupt_status_get_clr( ucTimerChannel );\r
- NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );\r
- NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
- NVIC_EnableIRQ( TIMER0_IRQn );\r
+ NVIC_SetPriority( GIRQ23_IRQn, ucTimerChannel );\r
+ NVIC_ClearPendingIRQ( GIRQ23_IRQn );\r
+ NVIC_EnableIRQ( GIRQ23_IRQn );\r
btimer_start( ucTimerChannel );\r
}\r
\r
\r
void vPortSetupTimerInterrupt( void )\r
{\r
- ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
+ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
\r
/* Set up the hibernation timer to start at the value required by the\r
tick interrupt. */\r
lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION;\r
\r
- /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */\r
- lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT;\r
+ /* Enable the HTIMER interrupt in the aggregated GIR17 block. */\r
+ lpEC_GIRQ17_SOURCE = lpGIRQ17_BIT_HTIMER;\r
+ lpEC_GIRQ17_ENABLE_CLEAR = lpGIRQ17_BIT_HTIMER;\r
+ lpBLOCK_ENABLE_SET = lpHTIMER_GIRQ_BLOCK;\r
+ lpEC_GIRQ17_ENABLE_SET = lpGIRQ17_BIT_HTIMER;\r
\r
/* The hibernation timer is not an auto-reload timer, so gets reset\r
from within the ISR itself. For that reason it's interrupt is set\r
to the highest possible priority to ensure clock slippage is minimised. */\r
- NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
- NVIC_ClearPendingIRQ( HTIMER_IRQn );\r
- NVIC_EnableIRQ( HTIMER_IRQn );\r
+ NVIC_SetPriority( GIRQ17_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_ClearPendingIRQ( GIRQ17_IRQn );\r
+ NVIC_EnableIRQ( GIRQ17_IRQn );\r
\r
/* A basic timer is also started, purely for test purposes. Its only\r
purpose is to bring the CPU out of its sleep mode by an interrupt other\r
/* Allow the application to define some post sleep processing. */\r
configPOST_SLEEP_PROCESSING( xModifiableIdleTime );\r
\r
- /* Stop the hibernation timer. Again, the time the tiemr is stopped\r
+ /* Stop the hibernation timer. Again, the time the timer is stopped\r
for is accounted for as best it can be, but using the tickless mode\r
will inevitably result in some tiny drift of the time maintained by the\r
kernel with respect to calendar time. Take the count value first as\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void NVIC_Handler_TMR0( void )\r
+void NVIC_Handler_GIRQ23( void )\r
{\r
- /* This timer is used for test purposes. Its only function is to\r
- generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
- brought out of sleep by a means other than the tick interrupt. */\r
-}\r
-/*-----------------------------------------------------------*/\r
+static volatile uint32_t ulTimerCounts = 0;\r
\r
+ /* The low power demo is using aggregated interrupts, so although in the\r
+ demo btimer 0 is the only peripheral that will generate interrupts on\r
+ this vector, in a real application it would be necessary to first check the\r
+ interrupt source. */\r
+ if( ( lpEC_GIRQ23_SOURCE & lpGIRQ23_BIT_TIMER0 ) != 0 )\r
+ {\r
+ /* Btimer0 interrupted. Clear the interrupt. */\r
+ lpEC_GIRQ23_SOURCE = lpGIRQ23_BIT_TIMER0;\r
\r
-#endif /* configCREATE_LOW_POWER_DEMO */\r
+ /* This timer is used for test purposes. Its only function is to\r
+ generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
+ brought out of sleep by a means other than the tick interrupt. */\r
+ ulTimerCounts++;\r
+ }\r
+ else\r
+ {\r
+ /* Don't expect any other interrupts to use this vector in this\r
+ demo. Force an assert. */\r
+ configASSERT( lpEC_GIRQ23_SOURCE == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
+#endif /* configCREATE_LOW_POWER_DEMO == 1 */\r
projects / freertos / blobdiff