--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * ARM_REG.h\r
+ * This is the header to define Cortex-M3 system control & status registers\r
+ **********************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/ARM_REG.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2016/09/22 08:03:49 $\r
+ * AUTHOR: $Author: pramans $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+/******************************************************************************/\r
+/** @defgroup ARM_REG ARM_REG\r
+ * @{\r
+ */\r
+\r
+/** @file ARM_REG.h\r
+* \brief ARM Cortex-M3 registers header file\r
+* \author KBCEC Team\r
+* \r
+* This file contains ARM Cortex-M3 system control & status registers.\r
+******************************************************************************/ \r
+#ifndef ARM_REG_H_\r
+#define ARM_REG_H_\r
+\r
+#define REG8(x) (*((volatile unsigned char *)(x)))\r
+#define REG16(x) (*((volatile unsigned short *)(x)))\r
+#define REG32(x) (*((volatile unsigned long *)(x)))\r
+\r
+/* NVIC Registers */\r
+#define NVIC_INT_TYPE REG32(0xE000E004)\r
+#define NVIC_AUX_ACTLR REG32(0xE000E008)\r
+ #define WR_BUF_DISABLE (1 << 1)\r
+#define NVIC_ST_CTRL REG32(0xE000E010)\r
+ #define ST_ENABLE (1 << 0)\r
+ #define ST_TICKINT (1 << 1)\r
+ #define ST_CLKSOURCE (1 << 2)\r
+ #define ST_COUNTFLAG (1 << 3)\r
+#define NVIC_ST_RELOAD REG32(0xE000E014)\r
+#define NVIC_ST_CURRENT REG32(0xE000E018)\r
+#define NVIC_ST_CALIB REG32(0xE000E01C)\r
+#define NVIC_ENABLE0 REG32(0xE000E100)\r
+#define NVIC_ENABLE1 REG32(0xE000E104)\r
+#define NVIC_ENABLE2 REG32(0xE000E108)\r
+#define NVIC_ENABLE3 REG32(0xE000E10C)\r
+#define NVIC_ENABLE4 REG32(0xE000E110)\r
+#define NVIC_ENABLE5 REG32(0xE000E114)\r
+#define NVIC_ENABLE6 REG32(0xE000E118)\r
+#define NVIC_ENABLE7 REG32(0xE000E11C)\r
+#define NVIC_DISABLE0 REG32(0xE000E180)\r
+#define NVIC_DISABLE1 REG32(0xE000E184)\r
+#define NVIC_DISABLE2 REG32(0xE000E188)\r
+#define NVIC_DISABLE3 REG32(0xE000E18C)\r
+#define NVIC_DISABLE4 REG32(0xE000E190)\r
+#define NVIC_DISABLE5 REG32(0xE000E194)\r
+#define NVIC_DISABLE6 REG32(0xE000E198)\r
+#define NVIC_DISABLE7 REG32(0xE000E19C)\r
+#define NVIC_PEND0 REG32(0xE000E200)\r
+#define NVIC_PEND1 REG32(0xE000E204)\r
+#define NVIC_PEND2 REG32(0xE000E208)\r
+#define NVIC_PEND3 REG32(0xE000E20C)\r
+#define NVIC_PEND4 REG32(0xE000E210)\r
+#define NVIC_PEND5 REG32(0xE000E214)\r
+#define NVIC_PEND6 REG32(0xE000E218)\r
+#define NVIC_PEND7 REG32(0xE000E21C)\r
+#define NVIC_UNPEND0 REG32(0xE000E280)\r
+#define NVIC_UNPEND1 REG32(0xE000E284)\r
+#define NVIC_UNPEND2 REG32(0xE000E288)\r
+#define NVIC_UNPEND3 REG32(0xE000E28C)\r
+#define NVIC_UNPEND4 REG32(0xE000E290)\r
+#define NVIC_UNPEND5 REG32(0xE000E294)\r
+#define NVIC_UNPEND6 REG32(0xE000E298)\r
+#define NVIC_UNPEND7 REG32(0xE000E29C)\r
+#define NVIC_ACTIVE0 REG32(0xE000E300)\r
+#define NVIC_ACTIVE1 REG32(0xE000E304)\r
+#define NVIC_ACTIVE2 REG32(0xE000E308)\r
+#define NVIC_ACTIVE3 REG32(0xE000E30C)\r
+#define NVIC_ACTIVE4 REG32(0xE000E310)\r
+#define NVIC_ACTIVE5 REG32(0xE000E314)\r
+#define NVIC_ACTIVE6 REG32(0xE000E318)\r
+#define NVIC_ACTIVE7 REG32(0xE000E31C)\r
+#define NVIC_PRI0 REG32(0xE000E400)\r
+#define NVIC_PRI1 REG32(0xE000E404)\r
+#define NVIC_PRI2 REG32(0xE000E408)\r
+#define NVIC_PRI3 REG32(0xE000E40C)\r
+#define NVIC_PRI4 REG32(0xE000E410)\r
+#define NVIC_PRI5 REG32(0xE000E414)\r
+#define NVIC_PRI6 REG32(0xE000E418)\r
+#define NVIC_PRI7 REG32(0xE000E41C)\r
+#define NVIC_PRI8 REG32(0xE000E420)\r
+#define NVIC_PRI9 REG32(0xE000E424)\r
+#define NVIC_PRI10 REG32(0xE000E428)\r
+#define NVIC_PRI11 REG32(0xE000E42C)\r
+#define NVIC_PRI12 REG32(0xE000E430)\r
+#define NVIC_PRI13 REG32(0xE000E434)\r
+#define NVIC_PRI14 REG32(0xE000E438)\r
+#define NVIC_PRI15 REG32(0xE000E43C)\r
+#define NVIC_PRI16 REG32(0xE000E440)\r
+#define NVIC_PRI17 REG32(0xE000E444)\r
+#define NVIC_PRI18 REG32(0xE000E448)\r
+#define NVIC_PRI19 REG32(0xE000E44C)\r
+#define NVIC_PRI20 REG32(0xE000E450)\r
+#define NVIC_PRI21 REG32(0xE000E454)\r
+#define NVIC_PRI22 REG32(0xE000E458)\r
+#define NVIC_PRI23 REG32(0xE000E45C)\r
+#define NVIC_PRI24 REG32(0xE000E460)\r
+#define NVIC_PRI25 REG32(0xE000E464)\r
+#define NVIC_PRI26 REG32(0xE000E468)\r
+#define NVIC_PRI27 REG32(0xE000E46C)\r
+#define NVIC_PRI28 REG32(0xE000E470)\r
+#define NVIC_PRI29 REG32(0xE000E474)\r
+#define NVIC_PRI30 REG32(0xE000E478)\r
+#define NVIC_PRI31 REG32(0xE000E47C)\r
+#define NVIC_PRI32 REG32(0xE000E480)\r
+#define NVIC_PRI33 REG32(0xE000E484)\r
+#define NVIC_PRI34 REG32(0xE000E488)\r
+#define NVIC_PRI35 REG32(0xE000E48C)\r
+#define NVIC_PRI36 REG32(0xE000E490)\r
+#define NVIC_PRI37 REG32(0xE000E494)\r
+#define NVIC_PRI38 REG32(0xE000E498)\r
+#define NVIC_PRI39 REG32(0xE000E49C)\r
+#define NVIC_PRI40 REG32(0xE000E4A0)\r
+#define NVIC_PRI41 REG32(0xE000E4A4)\r
+#define NVIC_PRI42 REG32(0xE000E4A8)\r
+#define NVIC_PRI43 REG32(0xE000E4AC)\r
+#define NVIC_PRI44 REG32(0xE000E4B0)\r
+#define NVIC_PRI45 REG32(0xE000E4B4)\r
+#define NVIC_PRI46 REG32(0xE000E4B8)\r
+#define NVIC_PRI47 REG32(0xE000E4BC)\r
+#define NVIC_PRI48 REG32(0xE000E4C0)\r
+#define NVIC_PRI49 REG32(0xE000E4C4)\r
+#define NVIC_PRI50 REG32(0xE000E4C8)\r
+#define NVIC_PRI51 REG32(0xE000E4CC)\r
+#define NVIC_PRI52 REG32(0xE000E4D0)\r
+#define NVIC_PRI53 REG32(0xE000E4D4)\r
+#define NVIC_PRI54 REG32(0xE000E4D8)\r
+#define NVIC_PRI55 REG32(0xE000E4DC)\r
+#define NVIC_PRI56 REG32(0xE000E4E0)\r
+#define NVIC_PRI57 REG32(0xE000E4E4)\r
+#define NVIC_PRI58 REG32(0xE000E4E8)\r
+#define NVIC_PRI59 REG32(0xE000E4EC)\r
+#define NVIC_CPUID REG32(0xE000ED00)\r
+#define NVIC_INT_CTRL REG32(0xE000ED04)\r
+#define NVIC_VECT_TABLE REG32(0xE000ED08)\r
+#define NVIC_AP_INT_RST REG32(0xE000ED0C)\r
+#define NVIC_SYS_CTRL REG32(0xE000ED10)\r
+#define NVIC_CFG_CTRL REG32(0xE000ED14)\r
+#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)\r
+#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)\r
+#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)\r
+#define NVIC_SYS_H_CTRL REG32(0xE000ED24)\r
+#define NVIC_FAULT_STA REG32(0xE000ED28)\r
+#define NVIC_HARD_F_STA REG32(0xE000ED2C)\r
+#define NVIC_DBG_F_STA REG32(0xE000ED30)\r
+#define NVIC_MM_F_ADR REG32(0xE000ED34)\r
+#define NVIC_BUS_F_ADR REG32(0xE000ED38)\r
+#define NVIC_SW_TRIG REG32(0xE000EF00)\r
+\r
+/* MPU Registers */\r
+#define MPU_TYPE REG32(0xE000ED90)\r
+#define MPU_CTRL REG32(0xE000ED94)\r
+#define MPU_RG_NUM REG32(0xE000ED98)\r
+#define MPU_RG_ADDR REG32(0xE000ED9C)\r
+#define MPU_RG_AT_SZ REG32(0xE000EDA0)\r
+\r
+\r
+#endif /* #ifndef ARM_REG_H_ */\r
+\r
+/** @}\r
+ */\r
projects / freertos / blobdiff