--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Renamed ecia_init to interrupt_init\r
+******************************************************************************/\r
+/** @file interrupt.h\r
+* \brief Interrupt Header File\r
+* \author jvasanth\r
+* \r
+* This file implements the Interrupt Module Header file \r
+******************************************************************************/\r
+\r
+/** @defgroup Interrupt\r
+ * @{\r
+ */\r
+\r
+#ifndef _INTERRUPT_H\r
+#define _INTERRUPT_H\r
+\r
+// GIRQ IDs for EC Interrupt Aggregator\r
+enum MEC_GIRQ_IDS\r
+{\r
+ MEC_GIRQ08_ID = 0,\r
+ MEC_GIRQ09_ID, \r
+ MEC_GIRQ10_ID, \r
+ MEC_GIRQ11_ID, \r
+ MEC_GIRQ12_ID, \r
+ MEC_GIRQ13_ID, \r
+ MEC_GIRQ14_ID, \r
+ MEC_GIRQ15_ID, \r
+ MEC_GIRQ16_ID, \r
+ MEC_GIRQ17_ID, \r
+ MEC_GIRQ18_ID, \r
+ MEC_GIRQ19_ID, \r
+ MEC_GIRQ20_ID, \r
+ MEC_GIRQ21_ID, \r
+ MEC_GIRQ22_ID, \r
+ MEC_GIRQ23_ID, \r
+ MEC_GIRQ_ID_MAX\r
+};\r
+\r
+//Bitmask of GIRQ in ECIA Block Registers\r
+#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))\r
+#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) \r
+#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) \r
+#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) \r
+#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) \r
+#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) \r
+#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) \r
+#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) \r
+#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) \r
+#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) \r
+#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) \r
+#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) \r
+#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) \r
+#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) \r
+#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) \r
+#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) \r
+\r
+#define INTERRUPT_MODE_ALL_AGGREGATED (0u)\r
+#define INTERRUPT_MODE_DIRECT (1u)\r
+\r
+// Bit map of GIRQs whose sources can be directly connected to the NVIC\r
+// GIRQs 13 - 19, 21, 23, 24-26\r
+#define ECIA_GIRQ_DIRECT_BITMAP (0x07AFE000ul)\r
+\r
+/*\r
+ * n = b[7:0] = zero-based direct mapped NVIC ID\r
+ * m = b[15:8] = zero-based aggregated NVIC ID\r
+ * a = b[23:16] = block Aggregator register block ID\r
+ * b = b[31:24] = block bit position in Aggregator registers\r
+*/\r
+#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \\r
+ (((uint32_t)(m)&0xFFul)<<8u) + \\r
+ ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \\r
+ (((uint32_t)(b)&0x1Ful)<<24))\r
+\r
+#define ECIA_NVIC_ID_BITPOS (0u)\r
+#define ECIA_IA_NVIC_ID_BITPOS (8u)\r
+#define ECIA_GIRQ_ID_BITPOS (16u)\r
+#define ECIA_GIRQ_BIT_BITPOS (24u)\r
+\r
+//\r
+// GIRQ08\r
+//\r
+#define GPIO_0140_IROUTE IROUTE(0,8,0,0)\r
+#define GPIO_0141_IROUTE IROUTE(1,8,0,0)\r
+#define GPIO_0142_IROUTE IROUTE(2,8,0,0)\r
+#define GPIO_0143_IROUTE IROUTE(3,8,0,0)\r
+#define GPIO_0144_IROUTE IROUTE(4,8,0,0)\r
+#define GPIO_0145_IROUTE IROUTE(5,8,0,0)\r
+#define GPIO_0147_IROUTE IROUTE(7,8,0,0)\r
+//\r
+#define GPIO_0150_IROUTE IROUTE(8,8,0,0)\r
+#define GPIO_0151_IROUTE IROUTE(9,8,0,0)\r
+#define GPIO_0152_IROUTE IROUTE(10,8,0,0)\r
+#define GPIO_0153_IROUTE IROUTE(11,8,0,0)\r
+#define GPIO_0154_IROUTE IROUTE(12,8,0,0)\r
+#define GPIO_0155_IROUTE IROUTE(13,8,0,0)\r
+#define GPIO_0156_IROUTE IROUTE(14,8,0,0)\r
+#define GPIO_0157_IROUTE IROUTE(15,8,0,0)\r
+//\r
+#define GPIO_0160_IROUTE IROUTE(16,8,0,0)\r
+#define GPIO_0161_IROUTE IROUTE(17,8,0,0)\r
+#define GPIO_0162_IROUTE IROUTE(18,8,0,0)\r
+#define GPIO_0163_IROUTE IROUTE(19,8,0,0)\r
+#define GPIO_0164_IROUTE IROUTE(20,8,0,0)\r
+#define GPIO_0165_IROUTE IROUTE(21,8,0,0)\r
+#define GPIO_0166_IROUTE IROUTE(22,8,0,0)\r
+#define GPIO_0167_IROUTE IROUTE(23,8,0,0)\r
+\r
+#define GPIO_0170_IROUTE IROUTE(24,8,0,0)\r
+#define GPIO_0171_IROUTE IROUTE(25,8,0,0)\r
+#define GPIO_0172_IROUTE IROUTE(26,8,0,0)\r
+#define GPIO_0173_IROUTE IROUTE(27,8,0,0)\r
+#define GPIO_0174_IROUTE IROUTE(28,8,0,0)\r
+#define GPIO_0175_IROUTE IROUTE(29,8,0,0)\r
+#define GPIO_0176_IROUTE IROUTE(30,8,0,0)\r
+\r
+//\r
+// GIRQ09\r
+//\r
+#define GPIO_0100_IROUTE IROUTE(0,9,1,1)\r
+#define GPIO_0101_IROUTE IROUTE(1,9,1,1)\r
+#define GPIO_0102_IROUTE IROUTE(2,9,1,1)\r
+#define GPIO_0103_IROUTE IROUTE(3,9,1,1)\r
+#define GPIO_0104_IROUTE IROUTE(4,9,1,1)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,1,1)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,1,1)\r
+#define GPIO_0107_IROUTE IROUTE(7,9,1,1)\r
+//\r
+#define GPIO_0110_IROUTE IROUTE(8,9,1,1)\r
+#define GPIO_0111_IROUTE IROUTE(9,9,1,1)\r
+#define GPIO_0112_IROUTE IROUTE(10,9,1,1)\r
+#define GPIO_0113_IROUTE IROUTE(11,9,1,1)\r
+#define GPIO_0114_IROUTE IROUTE(12,9,1,1)\r
+#define GPIO_0115_IROUTE IROUTE(13,9,1,1)\r
+#define GPIO_0116_IROUTE IROUTE(14,9,1,1)\r
+#define GPIO_0117_IROUTE IROUTE(15,9,1,1)\r
+//\r
+#define GPIO_0120_IROUTE IROUTE(16,9,1,1)\r
+#define GPIO_0121_IROUTE IROUTE(17,9,1,1)\r
+#define GPIO_0122_IROUTE IROUTE(18,9,1,1)\r
+#define GPIO_0124_IROUTE IROUTE(20,9,1,1)\r
+#define GPIO_0125_IROUTE IROUTE(21,9,1,1)\r
+#define GPIO_0126_IROUTE IROUTE(22,9,1,1)\r
+#define GPIO_0127_IROUTE IROUTE(23,9,1,1)\r
+//\r
+#define GPIO_0130_IROUTE IROUTE(24,9,1,1)\r
+#define GPIO_0131_IROUTE IROUTE(25,9,1,1)\r
+#define GPIO_0132_IROUTE IROUTE(26,9,1,1)\r
+#define GPIO_0133_IROUTE IROUTE(27,9,1,1)\r
+#define GPIO_0134_IROUTE IROUTE(28,9,1,1)\r
+#define GPIO_0135_IROUTE IROUTE(29,9,1,1)\r
+#define GPIO_0136_IROUTE IROUTE(30,9,1,1)\r
+\r
+//\r
+// GIRQ10\r
+//\r
+#define GPIO_0040_IROUTE IROUTE(0,10,2,2)\r
+#define GPIO_0041_IROUTE IROUTE(1,10,2,2)\r
+#define GPIO_0042_IROUTE IROUTE(2,10,2,2)\r
+#define GPIO_0043_IROUTE IROUTE(3,10,2,2)\r
+#define GPIO_0044_IROUTE IROUTE(4,10,2,2)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,2,2)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,2,2)\r
+#define GPIO_0047_IROUTE IROUTE(7,10,2,2)\r
+//\r
+#define GPIO_0050_IROUTE IROUTE(8,10,2,2)\r
+#define GPIO_0051_IROUTE IROUTE(9,10,2,2)\r
+#define GPIO_0052_IROUTE IROUTE(10,10,2,2)\r
+#define GPIO_0053_IROUTE IROUTE(11,10,2,2)\r
+#define GPIO_0054_IROUTE IROUTE(12,10,2,2)\r
+#define GPIO_0055_IROUTE IROUTE(13,10,2,2)\r
+#define GPIO_0056_IROUTE IROUTE(14,10,2,2)\r
+#define GPIO_0057_IROUTE IROUTE(15,10,2,2)\r
+//\r
+#define GPIO_0060_IROUTE IROUTE(16,10,2,2)\r
+#define GPIO_0061_IROUTE IROUTE(17,10,2,2)\r
+#define GPIO_0062_IROUTE IROUTE(18,10,2,2)\r
+#define GPIO_0063_IROUTE IROUTE(19,10,2,2)\r
+#define GPIO_0064_IROUTE IROUTE(20,10,2,2)\r
+#define GPIO_0065_IROUTE IROUTE(21,10,2,2)\r
+#define GPIO_0066_IROUTE IROUTE(22,10,2,2)\r
+#define GPIO_0067_IROUTE IROUTE(23,10,2,2)\r
+//\r
+#define GPIO_0070_IROUTE IROUTE(24,10,2,2)\r
+#define GPIO_0071_IROUTE IROUTE(25,10,2,2)\r
+#define GPIO_0072_IROUTE IROUTE(26,10,2,2)\r
+#define GPIO_0073_IROUTE IROUTE(27,10,2,2)\r
+#define GPIO_0074_IROUTE IROUTE(28,10,2,2)\r
+#define GPIO_0075_IROUTE IROUTE(29,10,2,2)\r
+#define GPIO_0076_IROUTE IROUTE(30,10,2,2)\r
+\r
+//\r
+// GIRQ11\r
+//\r
+#define GPIO_0000_IROUTE IROUTE(0,11,3,3)\r
+#define GPIO_0001_IROUTE IROUTE(1,11,3,3)\r
+#define GPIO_0002_IROUTE IROUTE(2,11,3,3)\r
+#define GPIO_0003_IROUTE IROUTE(3,11,3,3)\r
+#define GPIO_0004_IROUTE IROUTE(4,11,3,3)\r
+#define GPIO_0005_IROUTE IROUTE(5,11,3,3)\r
+#define GPIO_0006_IROUTE IROUTE(6,11,3,3)\r
+#define GPIO_0007_IROUTE IROUTE(7,11,3,3)\r
+//\r
+#define GPIO_0010_IROUTE IROUTE(8,11,3,3)\r
+#define GPIO_0011_IROUTE IROUTE(9,11,3,3)\r
+#define GPIO_0012_IROUTE IROUTE(10,11,3,3)\r
+#define GPIO_0013_IROUTE IROUTE(11,11,3,3)\r
+#define GPIO_0014_IROUTE IROUTE(12,11,3,3)\r
+#define GPIO_0015_IROUTE IROUTE(13,11,3,3)\r
+#define GPIO_0016_IROUTE IROUTE(14,11,3,3)\r
+#define GPIO_0017_IROUTE IROUTE(15,11,3,3)\r
+//\r
+#define GPIO_0020_IROUTE IROUTE(16,11,3,3)\r
+#define GPIO_0021_IROUTE IROUTE(17,11,3,3)\r
+#define GPIO_0022_IROUTE IROUTE(18,11,3,3)\r
+#define GPIO_0023_IROUTE IROUTE(19,11,3,3)\r
+#define GPIO_0024_IROUTE IROUTE(20,11,3,3)\r
+#define GPIO_0025_IROUTE IROUTE(21,11,3,3)\r
+#define GPIO_0026_IROUTE IROUTE(22,11,3,3)\r
+#define GPIO_0027_IROUTE IROUTE(23,11,3,3)\r
+//\r
+#define GPIO_0030_IROUTE IROUTE(24,11,3,3)\r
+#define GPIO_0031_IROUTE IROUTE(25,11,3,3)\r
+#define GPIO_0032_IROUTE IROUTE(26,11,3,3)\r
+#define GPIO_0033_IROUTE IROUTE(27,11,3,3)\r
+#define GPIO_0034_IROUTE IROUTE(28,11,3,3)\r
+#define GPIO_0035_IROUTE IROUTE(29,11,3,3)\r
+#define GPIO_0036_IROUTE IROUTE(30,11,3,3)\r
+\r
+\r
+// GIRQ12\r
+//\r
+#define GPIO_0200_IROUTE IROUTE(0,12,4,4)\r
+#define GPIO_0201_IROUTE IROUTE(1,12,4,4)\r
+#define GPIO_0202_IROUTE IROUTE(2,12,4,4)\r
+#define GPIO_0203_IROUTE IROUTE(3,12,4,4)\r
+#define GPIO_0204_IROUTE IROUTE(4,12,4,4)\r
+#define GPIO_0205_IROUTE IROUTE(5,12,4,4)\r
+#define GPIO_0206_IROUTE IROUTE(6,12,4,4)\r
+#define GPIO_0207_IROUTE IROUTE(7,12,4,4)\r
+//\r
+#define GPIO_0210_IROUTE IROUTE(8,12,4,4)\r
+#define GPIO_0211_IROUTE IROUTE(9,12,4,4)\r
+#define GPIO_0212_IROUTE IROUTE(10,12,4,4)\r
+#define GPIO_0213_IROUTE IROUTE(11,12,4,4)\r
+#define GPIO_0214_IROUTE IROUTE(12,12,4,4)\r
+#define GPIO_0215_IROUTE IROUTE(13,12,4,4)\r
+#define GPIO_0216_IROUTE IROUTE(14,12,4,4)\r
+#define GPIO_0217_IROUTE IROUTE(15,12,4,4)\r
+//\r
+#define GPIO_0220_IROUTE IROUTE(16,12,4,4)\r
+#define GPIO_0221_IROUTE IROUTE(17,12,4,4)\r
+#define GPIO_0222_IROUTE IROUTE(18,12,4,4)\r
+#define GPIO_0223_IROUTE IROUTE(19,12,4,4)\r
+#define GPIO_0224_IROUTE IROUTE(20,12,4,4)\r
+#define GPIO_0225_IROUTE IROUTE(21,12,4,4)\r
+#define GPIO_0226_IROUTE IROUTE(22,12,4,4)\r
+#define GPIO_0227_IROUTE IROUTE(23,12,4,4)\r
+//\r
+#define GPIO_0230_IROUTE IROUTE(24,12,4,4)\r
+#define GPIO_0231_IROUTE IROUTE(25,12,4,4)\r
+#define GPIO_0232_IROUTE IROUTE(26,12,4,4)\r
+#define GPIO_0233_IROUTE IROUTE(27,12,4,4)\r
+#define GPIO_0234_IROUTE IROUTE(28,12,4,4)\r
+#define GPIO_0235_IROUTE IROUTE(29,12,4,4)\r
+#define GPIO_0236_IROUTE IROUTE(30,12,4,4)\r
+\r
+\r
+\r
+//\r
+// GIRQ13\r
+//\r
+#define SMB0_IROUTE IROUTE(0,13,5,20)\r
+#define SMB1_IROUTE IROUTE(1,13,5,21)\r
+#define SMB2_IROUTE IROUTE(2,13,5,22)\r
+#define SMB3_IROUTE IROUTE(3,13,5,23)\r
+\r
+//\r
+// GIRQ14\r
+//\r
+#define DMA0_IROUTE IROUTE(0,14,6,24)\r
+#define DMA1_IROUTE IROUTE(1,14,6,25)\r
+#define DMA2_IROUTE IROUTE(2,14,6,26)\r
+#define DMA3_IROUTE IROUTE(3,14,6,27)\r
+#define DMA4_IROUTE IROUTE(4,14,6,28)\r
+#define DMA5_IROUTE IROUTE(5,14,6,29)\r
+#define DMA6_IROUTE IROUTE(6,14,6,30)\r
+#define DMA7_IROUTE IROUTE(7,14,6,31)\r
+#define DMA8_IROUTE IROUTE(8,14,6,33)\r
+#define DMA9_IROUTE IROUTE(9,14,6,33)\r
+#define DMA10_IROUTE IROUTE(10,14,6,34)\r
+#define DMA11_IROUTE IROUTE(11,14,6,35)\r
+#define DMA12_IROUTE IROUTE(12,14,6,36)\r
+#define DMA13_IROUTE IROUTE(13,14,6,37)\r
+\r
+\r
+//\r
+// GIRQ15\r
+//\r
+#define UART0_IROUTE IROUTE(0,15,7,40)\r
+#define UART1_IROUTE IROUTE(1,15,7,41)\r
+#define EMI0_IROUTE IROUTE(2,15,7,42)\r
+#define EMI1_IROUTE IROUTE(3,15,7,43)\r
+#define EMI2_IROUTE IROUTE(4,15,7,44)\r
+#define ACPI_EC0_IBF_IROUTE IROUTE(5,15,7,45)\r
+#define ACPI_EC0_OBF_IROUTE IROUTE(6,15,7,46)\r
+#define ACPI_EC1_IBF_IROUTE IROUTE(7,15,7,47)\r
+#define ACPI_EC1_OBF_IROUTE IROUTE(8,15,7,48)\r
+#define ACPI_EC2_IBF_IROUTE IROUTE(9,15,7,49)\r
+#define ACPI_EC2_OBF_IROUTE IROUTE(10,15,7,50)\r
+#define ACPI_EC3_IBF_IROUTE IROUTE(11,15,7,51)\r
+#define ACPI_EC3_OBF_IROUTE IROUTE(12,15,7,52)\r
+#define ACPI_EC4_IBF_IROUTE IROUTE(13,15,7,53)\r
+#define ACPI_EC4_OBF_IROUTE IROUTE(14,15,7,54)\r
+#define ACPI_PM1_CTL_IROUTE IROUTE(15,15,7,55)\r
+#define ACPI_PM1_EN_IROUTE IROUTE(16,15,7,56)\r
+#define ACPI_PM1_STS_IROUTE IROUTE(17,15,7,57)\r
+#define EM8042_OBF_IROUTE IROUTE(18,15,7,58)\r
+#define EM8042_IBF_IROUTE IROUTE(19,15,7,59)\r
+#define MBOX_IROUTE IROUTE(20,15,7,60)\r
+#define PORT80_DBG0_BDPINT_IROUTE IROUTE(22,15,7,62)\r
+#define PORT80_DBG1_BDPINT_IROUTE IROUTE(23,15,7,63)\r
+#define TEST_IROUTE IROUTE(24,15,7,64)\r
+\r
+//\r
+// GIRQ16\r
+//\r
+#define PKE_ERROR_IROUTE IROUTE(0,16,8,65)\r
+#define PKE_END_IROUTE IROUTE(1,16,8,66)\r
+#define RNG_IROUTE IROUTE(2,16,8,67)\r
+#define AES_IROUTE IROUTE(3,16,8,68)\r
+#define HASH_IROUTE IROUTE(4,16,8,69)\r
+\r
+//\r
+// GIRQ17\r
+//\r
+#define PECI_IROUTE IROUTE(0,17,9,70)\r
+#define TACH0_IROUTE IROUTE(1,17,9,71)\r
+#define TACH1_IROUTE IROUTE(2,17,9,72)\r
+#define TACH2_IROUTE IROUTE(3,17,9,73)\r
+#define RPM2PWM0_FAIL_IROUTE IROUTE(4,17,9,74)\r
+#define RPM2PWM0_STALL_IROUTE IROUTE(5,17,9,75)\r
+#define RPM2PWM1_FAIL_IROUTE IROUTE(6,17,9,76)\r
+#define RPM2PWM1_STALL_IROUTE IROUTE(7,17,9,77)\r
+#define ADC_SNGL_IROUTE IROUTE(8,17,9,78)\r
+#define ADC_RPT_IROUTE IROUTE(9,17,9,79)\r
+#define RC_ID0_IROUTE IROUTE(10,17,9,80)\r
+#define RC_ID1_IROUTE IROUTE(11,17,9,81)\r
+#define RC_ID2_IROUTE IROUTE(12,17,9,82)\r
+#define LED0_IROUTE IROUTE(13,17,9,83)\r
+#define LED1_IROUTE IROUTE(14,17,9,84)\r
+#define LED2_IROUTE IROUTE(15,17,9,85)\r
+#define LED3_IROUTE IROUTE(16,17,9,86)\r
+#define PHOT_IROUTE IROUTE(17,17,9,87)\r
+#define POWER_GUARD0_IROUTE IROUTE(18,17,9,88)\r
+#define POWER_GUARD1_IROUTE IROUTE(19,17,9,89)\r
+#define RTOS_SWI0_IROUTE IROUTE(25,17,9,9)\r
+#define RTOS_SWI1_IROUTE IROUTE(26,17,9,9)\r
+#define RTOS_SWI2_IROUTE IROUTE(27,17,9,9)\r
+#define RTOS_SWI3_IROUTE IROUTE(28,17,9,9)\r
+\r
+//\r
+// GIRQ18 \r
+//\r
+#define LPC_INT_ERR_IROUTE IROUTE(0,18,10,90)\r
+#define QMSPI_INT_IROUTE IROUTE(1,18,10,91)\r
+#define GP_SPI0_TXBE_STS_IROUTE IROUTE(2,18,10,92)\r
+#define GP_SPI0_RXBF_STS_IROUTE IROUTE(3,18,10,93)\r
+#define GP_SPI1_TXBE_STS_IROUTE IROUTE(4,18,10,94)\r
+#define GP_SPI1_RXBF_STS_IROUTE IROUTE(5,18,10,95)\r
+#define BCLINK0_BCM_ERR_IROUTE IROUTE(6,18,10,96)\r
+#define BCLINK0_BUSY_CLR_IROUTE IROUTE(7,18,10,97)\r
+#define BCLINK1_BCM_ERR_IROUTE IROUTE(8,18,10,98)\r
+#define BCLINK1_BUSY_CLR_IROUTE IROUTE(9,18,10,99)\r
+#define PS2_IFACE0_ACT_IROUTE IROUTE(10,18,10,100)\r
+#define PS2_IFACE1_ACT_IROUTE IROUTE(11,18,10,101)\r
+#define PS2_IFACE2_ACT_IROUTE IROUTE(12,18,10,102)\r
+#define EEPROM_IROUTE IROUTE(13,18,10,155)\r
+\r
+\r
+//\r
+// GIRQ19\r
+//\r
+#define ESPI_SLAVE_INTR_PC_IROUTE IROUTE(0,19,11,103)\r
+#define ESPI_SLAVE_INTR_BM1_IROUTE IROUTE(1,19,11,104)\r
+#define ESPI_SLAVE_INTR_BM2_IROUTE IROUTE(2,19,11,105)\r
+#define ESPI_SLAVE_INTR_LTR_IROUTE IROUTE(3,19,11,106)\r
+#define ESPI_SLAVE_INTR_OOB_UP_IROUTE IROUTE(4,19,11,107)\r
+#define ESPI_SLAVE_INTR_OOB_DN_IROUTE IROUTE(5,19,11,108)\r
+#define ESPI_SLAVE_INTR_FLASH_IROUTE IROUTE(6,19,11,109)\r
+#define ESPI_SLAVE_ESPI_RESET_IROUTE IROUTE(7,19,11,110)\r
+#define ESPI_SLAVE_VW_ENABLE_IROUTE IROUTE(8,19,11,156)\r
+\r
+//\r
+// GIRQ20\r
+//\r
+\r
+\r
+//\r
+// GIRQ21\r
+//\r
+#define RTOS_TIMER_IROUTE IROUTE(0,21,13,111)\r
+#define HTIMER0_IROUTE IROUTE(1,21,13,112)\r
+#define HTIMER1_IROUTE IROUTE(2,21,13,113)\r
+#define WEEK_ALARM_INT_IROUTE IROUTE(3,21,13,114)\r
+#define SUB_WEEK_ALARM_IN_IROUTE IROUTE(4,21,13,115)\r
+#define WEEK_ALARM_ONE_SECOND_IROUTE IROUTE(5,21,13,116)\r
+#define WEEK_ALARM_SUB_SECOND_IROUTE IROUTE(6,21,13,117)\r
+#define WEEK_ALARM_SYSPWR_PRES_IROUTE IROUTE(7,21,13,118)\r
+#define RTC_IROUTE IROUTE(8,21,13,119)\r
+#define RTC_ALARM_IROUTE IROUTE(9,21,13,120)\r
+#define VBAT_VCI_OVRD_IN_IROUTE IROUTE(10,21,13,121)\r
+#define VBAT_VCI_IN0_IROUTE IROUTE(11,21,13,122)\r
+#define VBAT_VCI_IN1_IROUTE IROUTE(12,21,13,123)\r
+#define VBAT_VCI_IN2_IROUTE IROUTE(13,21,13,124)\r
+#define VBAT_VCI_IN3_IROUTE IROUTE(14,21,13,125)\r
+#define VBAT_VCI_IN4_IROUTE IROUTE(15,21,13,126)\r
+#define VBAT_VCI_IN5_IROUTE IROUTE(16,21,13,127)\r
+#define VBAT_VCI_IN6_IROUTE IROUTE(17,21,13,128)\r
+#define PS2_0A_WK_IROUTE IROUTE(18,21,13,129)\r
+#define PS2_0B_WK_IROUTE IROUTE(19,21,13,130)\r
+#define PS2_1A_WK_IROUTE IROUTE(20,21,13,131)\r
+#define PS2_1B_WK_IROUTE IROUTE(21,21,13,132)\r
+#define PS2_2_WK_IROUTE IROUTE(22,21,13,133)\r
+#define ENVMON_IROUTE IROUTE(24,21,13,134)\r
+#define KSC_INT_IROUTE IROUTE(25,21,13,135)\r
+\r
+\r
+//\r
+// GIRQ22 (No Aggregated & No direct source, WAKE ONLY EVENTS)\r
+//\r
+#define LPC_WAKE_ONLY_IROUTE IROUTE(0,22,22,22)\r
+#define SMB0_WAKE_ONLY_IROUTE IROUTE(1,22,22,22)\r
+#define SMB1_WAKE_ONLY_IROUTE IROUTE(2,22,22,22)\r
+#define SMB2_WAKE_ONLY_IROUTE IROUTE(3,22,22,22)\r
+#define SMB3_WAKE_ONLY_IROUTE IROUTE(4,22,22,22)\r
+#define ESPI_WAKE_ONLY_IROUTE IROUTE(9,22,22,22)\r
+\r
+//\r
+// GIRQ23\r
+//\r
+#define BTMR0_IROUTE IROUTE(0,23,14,136)\r
+#define BTMR1_IROUTE IROUTE(1,23,14,137)\r
+#define BTMR2_IROUTE IROUTE(2,23,14,138)\r
+#define BTMR3_IROUTE IROUTE(3,23,14,139)\r
+#define BTMR4_IROUTE IROUTE(4,23,14,140)\r
+#define BTMR5_IROUTE IROUTE(5,23,14,141)\r
+#define CTIMER0_IROUTE IROUTE(6,23,14,142)\r
+#define CTIMER1_IROUTE IROUTE(7,23,14,143)\r
+#define CTIMER2_IROUTE IROUTE(8,23,14,144)\r
+#define CTIMER3_IROUTE IROUTE(9,23,14,145)\r
+#define CAP_TIMER_IROUTE IROUTE(10,23,14,146)\r
+#define CC_TIMER0_IROUTE IROUTE(11,23,14,147)\r
+#define CC_TIMER1_IROUTE IROUTE(12,23,14,148)\r
+#define CC_TIMER2_IROUTE IROUTE(13,23,14,149)\r
+#define CC_TIMER3_IROUTE IROUTE(14,23,14,150)\r
+#define CC_TIMER4_IROUTE IROUTE(15,23,14,151)\r
+#define CC_TIMER5_IROUTE IROUTE(16,23,14,152)\r
+#define CC_TIMER_CMP0_IROUTE IROUTE(17,23,14,153)\r
+#define CC_TIMER_CMP1_IROUTE IROUTE(18,23,14,154)\r
+\r
+//\r
+// GIRQ23\r
+//\r
+#define ESPI_SLAVE_VW00_SRC0_IROUTE IROUTE(0,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC1_IROUTE IROUTE(1,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC2_IROUTE IROUTE(2,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC3_IROUTE IROUTE(3,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC0_IROUTE IROUTE(4,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC1_IROUTE IROUTE(5,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC2_IROUTE IROUTE(6,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC3_IROUTE IROUTE(7,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC0_IROUTE IROUTE(8,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC1_IROUTE IROUTE(9,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC2_IROUTE IROUTE(10,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC3_IROUTE IROUTE(11,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC0_IROUTE IROUTE(12,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC1_IROUTE IROUTE(13,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC2_IROUTE IROUTE(14,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC3_IROUTE IROUTE(15,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC0_IROUTE IROUTE(16,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC1_IROUTE IROUTE(17,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC2_IROUTE IROUTE(18,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC3_IROUTE IROUTE(19,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC0_IROUTE IROUTE(20,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC1_IROUTE IROUTE(21,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC2_IROUTE IROUTE(22,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC3_IROUTE IROUTE(23,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC0_IROUTE IROUTE(24,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC1_IROUTE IROUTE(25,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC2_IROUTE IROUTE(26,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC3_IROUTE IROUTE(27,24,15,15)\r
+\r
+\r
+//\r
+// GIRQ25\r
+//\r
+#define ESPI_SLAVE_VW07_SRC0_IROUTE IROUTE(0,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC1_IROUTE IROUTE(1,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC2_IROUTE IROUTE(2,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC3_IROUTE IROUTE(3,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC0_IROUTE IROUTE(4,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC1_IROUTE IROUTE(5,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC2_IROUTE IROUTE(6,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC3_IROUTE IROUTE(7,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC0_IROUTE IROUTE(8,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC1_IROUTE IROUTE(9,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC2_IROUTE IROUTE(10,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC3_IROUTE IROUTE(11,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC0_IROUTE IROUTE(12,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC1_IROUTE IROUTE(13,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC2_IROUTE IROUTE(14,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC3_IROUTE IROUTE(15,25,15,15)\r
+\r
+//\r
+// GIRQ26\r
+//\r
+#define GPIO_0240_IROUTE IROUTE(0,26,17,17)\r
+#define GPIO_0241_IROUTE IROUTE(1,26,17,17)\r
+#define GPIO_0242_IROUTE IROUTE(2,26,17,17)\r
+#define GPIO_0243_IROUTE IROUTE(3,26,17,17)\r
+#define GPIO_0244_IROUTE IROUTE(4,26,17,17)\r
+#define GPIO_0245_IROUTE IROUTE(5,26,17,17)\r
+#define GPIO_0246_IROUTE IROUTE(6,26,17,17)\r
+#define GPIO_0247_IROUTE IROUTE(7,26,17,17)\r
+//\r
+#define GPIO_0250_IROUTE IROUTE(8,26,17,17)\r
+#define GPIO_0251_IROUTE IROUTE(9,26,17,17)\r
+#define GPIO_0252_IROUTE IROUTE(10,26,17,17)\r
+#define GPIO_0253_IROUTE IROUTE(11,26,17,17)\r
+#define GPIO_0254_IROUTE IROUTE(12,26,17,17)\r
+#define GPIO_0255_IROUTE IROUTE(13,26,17,17)\r
+#define GPIO_0256_IROUTE IROUTE(14,26,17,17)\r
+#define GPIO_0257_IROUTE IROUTE(15,26,17,17)\r
+//\r
+#define GPIO_0260_IROUTE IROUTE(16,26,17,17)\r
+#define GPIO_0261_IROUTE IROUTE(17,26,17,17)\r
+#define GPIO_0262_IROUTE IROUTE(18,26,17,17)\r
+#define GPIO_0263_IROUTE IROUTE(19,26,17,17)\r
+#define GPIO_0264_IROUTE IROUTE(20,26,17,17)\r
+#define GPIO_0265_IROUTE IROUTE(21,26,17,17)\r
+#define GPIO_0266_IROUTE IROUTE(22,26,17,17)\r
+#define GPIO_0267_IROUTE IROUTE(23,26,17,17)\r
+//\r
+#define GPIO_0270_IROUTE IROUTE(24,26,17,17)\r
+#define GPIO_0271_IROUTE IROUTE(25,26,17,17)\r
+#define GPIO_0272_IROUTE IROUTE(26,26,17,17)\r
+#define GPIO_0273_IROUTE IROUTE(27,26,17,17)\r
+#define GPIO_0274_IROUTE IROUTE(28,26,17,17)\r
+#define GPIO_0275_IROUTE IROUTE(29,26,17,17)\r
+#define GPIO_0276_IROUTE IROUTE(30,26,17,17)\r
+\r
+\r
+// GIRQ08 Bit Positions \r
+#define GIRQ08_GPIO_0140_BITPOS (0)\r
+#define GIRQ08_GPIO_0141_BITPOS (1)\r
+#define GIRQ08_GPIO_0142_BITPOS (2)\r
+#define GIRQ08_GPIO_0143_BITPOS (3)\r
+#define GIRQ08_GPIO_0144_BITPOS (4)\r
+#define GIRQ08_GPIO_0145_BITPOS (5)\r
+#define GIRQ08_GPIO_0146_BITPOS (6)\r
+#define GIRQ08_GPIO_0147_BITPOS (7)\r
+//\r
+#define GIRQ08_GPIO_0150_BITPOS (8)\r
+#define GIRQ08_GPIO_0151_BITPOS (9)\r
+#define GIRQ08_GPIO_0152_BITPOS (10)\r
+#define GIRQ08_GPIO_0153_BITPOS (11)\r
+#define GIRQ08_GPIO_0154_BITPOS (12)\r
+#define GIRQ08_GPIO_0155_BITPOS (13)\r
+#define GIRQ08_GPIO_0156_BITPOS (14) \r
+#define GIRQ08_GPIO_0157_BITPOS (15)\r
+//\r
+#define GIRQ08_GPIO_0160_BITPOS (16)\r
+#define GIRQ08_GPIO_0161_BITPOS (17)\r
+#define GIRQ08_GPIO_0162_BITPOS (18)\r
+#define GIRQ08_GPIO_0163_BITPOS (19)\r
+#define GIRQ08_GPIO_0164_BITPOS (20)\r
+#define GIRQ08_GPIO_0165_BITPOS (21)\r
+#define GIRQ08_GPIO_0166_BITPOS (22) \r
+#define GIRQ08_GPIO_0167_BITPOS (23)\r
+\r
+#define GIRQ08_GPIO_0170_BITPOS (24)\r
+#define GIRQ08_GPIO_0171_BITPOS (25)\r
+#define GIRQ08_GPIO_0172_BITPOS (26)\r
+#define GIRQ08_GPIO_0173_BITPOS (27)\r
+#define GIRQ08_GPIO_0174_BITPOS (28)\r
+#define GIRQ08_GPIO_0175_BITPOS (29)\r
+#define GIRQ08_GPIO_0176_BITPOS (30) \r
+\r
+//\r
+#define GIRQ08_MASK (0x7FFFFFFFul)\r
+#define GIRQ08_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ09 Bit Positions \r
+#define GIRQ09_GPIO_0100_BITPOS (0)\r
+#define GIRQ09_GPIO_0101_BITPOS (1)\r
+#define GIRQ09_GPIO_0102_BITPOS (2)\r
+#define GIRQ09_GPIO_0103_BITPOS (3)\r
+#define GIRQ09_GPIO_0104_BITPOS (4)\r
+#define GIRQ09_GPIO_0105_BITPOS (5)\r
+#define GIRQ09_GPIO_0106_BITPOS (6) \r
+#define GIRQ09_GPIO_0107_BITPOS (7)\r
+//\r
+#define GIRQ09_GPIO_0110_BITPOS (8)\r
+#define GIRQ09_GPIO_0111_BITPOS (9)\r
+#define GIRQ09_GPIO_0112_BITPOS (10)\r
+#define GIRQ09_GPIO_0113_BITPOS (11)\r
+#define GIRQ09_GPIO_0114_BITPOS (12)\r
+#define GIRQ09_GPIO_0115_BITPOS (13)\r
+#define GIRQ09_GPIO_0116_BITPOS (14) \r
+#define GIRQ09_GPIO_0117_BITPOS (15)\r
+//\r
+#define GIRQ09_GPIO_0120_BITPOS (16)\r
+#define GIRQ09_GPIO_0121_BITPOS (17)\r
+#define GIRQ09_GPIO_0122_BITPOS (18)\r
+#define GIRQ09_GPIO_0123_BITPOS (19)\r
+#define GIRQ09_GPIO_0124_BITPOS (20)\r
+#define GIRQ09_GPIO_0125_BITPOS (21)\r
+#define GIRQ09_GPIO_0126_BITPOS (22) \r
+#define GIRQ09_GPIO_0127_BITPOS (23)\r
+//\r
+#define GIRQ09_GPIO_0130_BITPOS (24)\r
+#define GIRQ09_GPIO_0131_BITPOS (25)\r
+#define GIRQ09_GPIO_0132_BITPOS (26)\r
+#define GIRQ09_GPIO_0133_BITPOS (27)\r
+#define GIRQ09_GPIO_0134_BITPOS (28)\r
+#define GIRQ09_GPIO_0135_BITPOS (29)\r
+#define GIRQ09_GPIO_0136_BITPOS (30) \r
+\r
+//\r
+#define GIRQ09_MASK (0x7FFFFFFFul)\r
+#define GIRQ09_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ10 Bit Positions \r
+#define GIRQ10_GPIO_0040_BITPOS (0)\r
+#define GIRQ10_GPIO_0041_BITPOS (1)\r
+#define GIRQ10_GPIO_0042_BITPOS (2)\r
+#define GIRQ10_GPIO_0043_BITPOS (3)\r
+#define GIRQ10_GPIO_0044_BITPOS (4)\r
+#define GIRQ10_GPIO_0045_BITPOS (5)\r
+#define GIRQ10_GPIO_0046_BITPOS (6) \r
+#define GIRQ10_GPIO_0047_BITPOS (7)\r
+//\r
+#define GIRQ10_GPIO_0050_BITPOS (8)\r
+#define GIRQ10_GPIO_0051_BITPOS (9)\r
+#define GIRQ10_GPIO_0052_BITPOS (10)\r
+#define GIRQ10_GPIO_0053_BITPOS (11)\r
+#define GIRQ10_GPIO_0054_BITPOS (12)\r
+#define GIRQ10_GPIO_0055_BITPOS (13)\r
+#define GIRQ10_GPIO_0056_BITPOS (14) \r
+#define GIRQ10_GPIO_0057_BITPOS (15)\r
+//\r
+#define GIRQ10_GPIO_0060_BITPOS (16)\r
+#define GIRQ10_GPIO_0061_BITPOS (17)\r
+#define GIRQ10_GPIO_0062_BITPOS (18)\r
+#define GIRQ10_GPIO_0063_BITPOS (19)\r
+#define GIRQ10_GPIO_0064_BITPOS (20)\r
+#define GIRQ10_GPIO_0065_BITPOS (21)\r
+#define GIRQ10_GPIO_0066_BITPOS (22) \r
+#define GIRQ10_GPIO_0067_BITPOS (23)\r
+//\r
+#define GIRQ10_GPIO_0070_BITPOS (24)\r
+#define GIRQ10_GPIO_0071_BITPOS (25)\r
+#define GIRQ10_GPIO_0072_BITPOS (26)\r
+#define GIRQ10_GPIO_0073_BITPOS (27)\r
+#define GIRQ10_GPIO_0074_BITPOS (28)\r
+#define GIRQ10_GPIO_0075_BITPOS (29)\r
+#define GIRQ10_GPIO_0076_BITPOS (30) \r
+\r
+//\r
+#define GIRQ10_MASK (0x7FFFFFFFul)\r
+#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ11 Bit Positions \r
+#define GIRQ11_GPIO_0000_BITPOS (0)\r
+#define GIRQ11_GPIO_0001_BITPOS (1)\r
+#define GIRQ11_GPIO_0002_BITPOS (2)\r
+#define GIRQ11_GPIO_0003_BITPOS (3)\r
+#define GIRQ11_GPIO_0004_BITPOS (4)\r
+#define GIRQ11_GPIO_0005_BITPOS (5)\r
+#define GIRQ11_GPIO_0006_BITPOS (6) \r
+#define GIRQ11_GPIO_0007_BITPOS (7)\r
+//\r
+#define GIRQ11_GPIO_0010_BITPOS (8)\r
+#define GIRQ11_GPIO_0011_BITPOS (9)\r
+#define GIRQ11_GPIO_0012_BITPOS (10)\r
+#define GIRQ11_GPIO_0013_BITPOS (11)\r
+#define GIRQ11_GPIO_0014_BITPOS (12)\r
+#define GIRQ11_GPIO_0015_BITPOS (13)\r
+#define GIRQ11_GPIO_0016_BITPOS (14) \r
+#define GIRQ11_GPIO_0017_BITPOS (15)\r
+//\r
+#define GIRQ11_GPIO_0020_BITPOS (16)\r
+#define GIRQ11_GPIO_0021_BITPOS (17)\r
+#define GIRQ11_GPIO_0022_BITPOS (18)\r
+#define GIRQ11_GPIO_0023_BITPOS (19)\r
+#define GIRQ11_GPIO_0024_BITPOS (20)\r
+#define GIRQ11_GPIO_0025_BITPOS (21)\r
+#define GIRQ11_GPIO_0026_BITPOS (22) \r
+#define GIRQ11_GPIO_0027_BITPOS (23)\r
+//\r
+#define GIRQ11_GPIO_0030_BITPOS (24)\r
+#define GIRQ11_GPIO_0031_BITPOS (25)\r
+#define GIRQ11_GPIO_0032_BITPOS (26)\r
+#define GIRQ11_GPIO_0033_BITPOS (27)\r
+#define GIRQ11_GPIO_0034_BITPOS (28)\r
+#define GIRQ11_GPIO_0035_BITPOS (29)\r
+#define GIRQ11_GPIO_0036_BITPOS (30) \r
+\r
+//\r
+#define GIRQ11_MASK (0x7FFFFFFFul)\r
+#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ12 Bit Positions \r
+#define GIRQ12_GPIO_0200_BITPOS (0)\r
+#define GIRQ12_GPIO_0201_BITPOS (1)\r
+#define GIRQ12_GPIO_0202_BITPOS (2)\r
+#define GIRQ12_GPIO_0203_BITPOS (3)\r
+#define GIRQ12_GPIO_0204_BITPOS (4)\r
+#define GIRQ12_GPIO_0205_BITPOS (5)\r
+#define GIRQ12_GPIO_0206_BITPOS (6) \r
+#define GIRQ12_GPIO_0207_BITPOS (7)\r
+//\r
+#define GIRQ12_GPIO_0210_BITPOS (8)\r
+#define GIRQ12_GPIO_0211_BITPOS (9)\r
+#define GIRQ12_GPIO_0212_BITPOS (10)\r
+#define GIRQ12_GPIO_0213_BITPOS (11)\r
+#define GIRQ12_GPIO_0214_BITPOS (12)\r
+#define GIRQ12_GPIO_0215_BITPOS (13)\r
+#define GIRQ12_GPIO_0216_BITPOS (14) \r
+#define GIRQ12_GPIO_0217_BITPOS (15)\r
+//\r
+#define GIRQ12_GPIO_0220_BITPOS (16)\r
+#define GIRQ12_GPIO_0221_BITPOS (17)\r
+#define GIRQ12_GPIO_0222_BITPOS (18)\r
+#define GIRQ12_GPIO_0223_BITPOS (19)\r
+#define GIRQ12_GPIO_0224_BITPOS (20)\r
+#define GIRQ12_GPIO_0225_BITPOS (21)\r
+#define GIRQ12_GPIO_0226_BITPOS (22) \r
+#define GIRQ12_GPIO_0227_BITPOS (23)\r
+//\r
+#define GIRQ12_GPIO_0230_BITPOS (24)\r
+#define GIRQ12_GPIO_0231_BITPOS (25)\r
+#define GIRQ12_GPIO_0232_BITPOS (26)\r
+#define GIRQ12_GPIO_0233_BITPOS (27)\r
+#define GIRQ12_GPIO_0234_BITPOS (28)\r
+#define GIRQ12_GPIO_0235_BITPOS (29)\r
+#define GIRQ12_GPIO_0236_BITPOS (30) \r
+\r
+//\r
+#define GIRQ12_MASK (0x7FFFFFFFul)\r
+#define GIRQ12_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+\r
+// GIRQ13 Bit Positions \r
+#define GIRQ13_SMBUS0_BITPOS (0)\r
+#define GIRQ13_SMBUS1_BITPOS (1)\r
+#define GIRQ13_SMBUS2_BITPOS (2)\r
+#define GIRQ13_SMBUS3_BITPOS (3)\r
+\r
+#define GIRQ13_MASK (0xFul)\r
+#define GIRQ13_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ14 Bit Positions \r
+#define GIRQ14_DMA0_BITPOS (0)\r
+#define GIRQ14_DMA1_BITPOS (1)\r
+#define GIRQ14_DMA2_BITPOS (2)\r
+#define GIRQ14_DMA3_BITPOS (3)\r
+#define GIRQ14_DMA4_BITPOS (4)\r
+#define GIRQ14_DMA5_BITPOS (5)\r
+#define GIRQ14_DMA6_BITPOS (6)\r
+#define GIRQ14_DMA7_BITPOS (7)\r
+#define GIRQ14_DMA8_BITPOS (8)\r
+#define GIRQ14_DMA9_BITPOS (9)\r
+#define GIRQ14_DMA10_BITPOS (10)\r
+#define GIRQ14_DMA11_BITPOS (11)\r
+#define GIRQ14_DMA12_BITPOS (12)\r
+#define GIRQ14_DMA13_BITPOS (13)\r
+//\r
+#define GIRQ14_MASK (0x3FFFul)\r
+#define GIRQ14_WAKE_CAPABLE_MASK (0x00000000ul)\r
+//\r
+\r
+\r
+// GIRQ15 Bit Positions \r
+#define GIRQ15_UART0_BITPOS (0)\r
+#define GIRQ15_UART1_BITPOS (1)\r
+#define GIRQ15_EMI0_BITPOS (2)\r
+#define GIRQ15_EMI1_BITPOS (3)\r
+#define GIRQ15_EMI2_BITPOS (4)\r
+#define GIRQ15_ACPI0_IBF_BITPOS (5)\r
+#define GIRQ15_ACPI0_OBF_BITPOS (6)\r
+#define GIRQ15_ACPI1_IBF_BITPOS (7)\r
+#define GIRQ15_ACPI1_OBF_BITPOS (8)\r
+#define GIRQ15_ACPI2_IBF_BITPOS (9)\r
+#define GIRQ15_ACPI2_OBF_BITPOS (10)\r
+#define GIRQ15_ACPI3_IBF_BITPOS (11)\r
+#define GIRQ15_ACPI3_OBF_BITPOS (12)\r
+#define GIRQ15_ACPI4_IBF_BITPOS (13)\r
+#define GIRQ15_ACPI4_OBF_BITPOS (14)\r
+#define GIRQ15_ACPI_PM1CTL_BITPOS (15)\r
+#define GIRQ15_ACPI_PM1EN_BITPOS (16)\r
+#define GIRQ15_ACPI_PM1STS_BITPOS (17)\r
+#define GIRQ15_MF8042_OBF_BITPOS (18)\r
+#define GIRQ15_MF8042_IBF_BITPOS (19)\r
+#define GIRQ15_MAILBOX_BITPOS (20)\r
+#define GIRQ15_PORT80_DBG0_BITPOS (22)\r
+#define GIRQ15_PORT80_DBG1_BITPOS (23)\r
+#define GIRQ15_TEST_BITPOS (24)\r
+\r
+//\r
+#define GIRQ15_MASK (0x1FFFFFFul)\r
+#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)\r
+//\r
+\r
+// GIRQ16 Bit Positions \r
+#define PKE_ERROR_BITPOS (0)\r
+#define PKE_END_BITPOS (1)\r
+#define RNG_BITPOS (2)\r
+#define AES_BITPOS (3)\r
+#define HASH_BITPOS (4)\r
+\r
+//\r
+#define GIRQ16_MASK (0x1Ful)\r
+#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)\r
+//\r
+\r
+// GIRQ17 Bit Positions \r
+#define GIRQ17_PECI_BITPOS (0)\r
+#define GIRQ17_TACH0_BITPOS (1)\r
+#define GIRQ17_TACH1_BITPOS (2)\r
+#define GIRQ17_TACH2_BITPOS (3)\r
+#define GIRQ17_RPM2PWM0_FAIL_BITPOS (4)\r
+#define GIRQ17_RPM2PWM0_STALL_BITPOS (5)\r
+#define GIRQ17_RPM2PWM1_FAIL_BITPOS (6)\r
+#define GIRQ17_RPM2PWM1_STALL_BITPOS (7)\r
+#define GIRQ17_ADC_INT0_BITPOS (8)\r
+#define GIRQ17_ADC_INT1_BITPOS (9)\r
+#define GIRQ17_RC_ID0_BITPOS (10)\r
+#define GIRQ17_RC_ID1_BITPOS (11)\r
+#define GIRQ17_RC_ID2_BITPOS (12)\r
+#define GIRQ17_LED0_BITPOS (13)\r
+#define GIRQ17_LED1_BITPOS (14)\r
+#define GIRQ17_LED2_BITPOS (15)\r
+#define GIRQ17_LED3_BITPOS (16)\r
+#define GIRQ17_PHOT_BITPOS (17)\r
+#define GIRQ17_PWRGUARD0_BITPOS (18)\r
+#define GIRQ17_PWRGUARD1_BITPOS (19)\r
+#define GIRQ17_RTOS_SWI0_BITPOS (25)\r
+#define GIRQ17_RTOS_SWI1_BITPOS (26)\r
+#define GIRQ17_RTOS_SWI2_BITPOS (27)\r
+#define GIRQ17_RTOS_SWI3_BITPOS (28)\r
+\r
+//\r
+#define GIRQ17_MASK (0x1E0FFFFFul)\r
+#define GIRQ17_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ18 Bit Positions\r
+#define GIRQ18_LPC_ERROR_BITPOS (0)\r
+#define GIRQ18_QMSPI_INT_BITPOS (1)\r
+#define GIRQ18_SPI0_TX_BITPOS (2)\r
+#define GIRQ18_SPI0_RX_BITPOS (3)\r
+#define GIRQ18_SPI1_TX_BITPOS (4)\r
+#define GIRQ18_SPI1_RX_BITPOS (5)\r
+#define GIRQ18_BCM0_BUSY_CLR_BITPOS (6)\r
+#define GIRQ18_BCM0_ERROR_BITPOS (7)\r
+#define GIRQ18_BCM1_BUSY_CLR_BITPOS (8)\r
+#define GIRQ18_BCM1_ERROR_BITPOS (9)\r
+#define GIRQ18_PS2_ACT0_BITPOS (10)\r
+#define GIRQ18_PS2_ACT1_BITPOS (11)\r
+#define GIRQ18_PS2_ACT2_BITPOS (12)\r
+#define GIRQ18_EEPROM_BITPOS (13)\r
+\r
+//\r
+#define GIRQ18_MASK (0x3FFFul)\r
+#define GIRQ18_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ19 Bit Positions \r
+#define GIRQ19_ESPI_INTR_PC_BITPOS (0)\r
+#define GIRQ19_ESPI_INTR_BM1_BITPOS (1)\r
+#define GIRQ19_ESPI_INTR_BM2_BITPOS (2)\r
+#define GIRQ19_ESPI_INTR_LTR_BITPOS (3)\r
+#define GIRQ19_ESPI_INTR_OOB_UP_BITPOS (4)\r
+#define GIRQ19_ESPI_INTR_OOB_DN_BITPOS (5)\r
+#define GIRQ19_ESPI_INTR_FLASH_BITPOS (6)\r
+#define GIRQ19_ESPI_RESET_BITPOS (7)\r
+#define GIRQ19_ESPI_VW_ENABLE_BITPOS (8)\r
+\r
+//\r
+#define GIRQ19_MASK (0x01FFul)\r
+#define GIRQ19_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ20 Bit Positions \r
+\r
+// \r
+#define GIRQ20_MASK (0x0ul)\r
+#define GIRQ20_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ21 Bit Positions \r
+#define GIRQ21_RTOS_TIMER_BITPOS (0)\r
+#define GIRQ21_HTIMER0_BITPOS (1)\r
+#define GIRQ21_HTIMER1_BITPOS (2)\r
+#define GIRQ21_WEEK_ALRM_INT_BITPOS (3)\r
+#define GIRQ21_SUB_WEEK_ALRM_INT_BITPOS (4)\r
+#define GIRQ21_ONE_SECOND_BITPOS (5)\r
+#define GIRQ21_SUB_SECOND_BITPOS (6)\r
+#define GIRQ21_SYSPWR_PRES_BITPOS (7)\r
+#define GIRQ21_RTC_BITPOS (8)\r
+#define GIRQ21_RTC_ALARM_BITPOS (9)\r
+#define GIRQ21_VBAT_VCI_OVRD_IN_BITPOS (10)\r
+#define GIRQ21_VBAT_VCI_IN0_BITPOS (11)\r
+#define GIRQ21_VBAT_VCI_IN1_BITPOS (12)\r
+#define GIRQ21_VBAT_VCI_IN2_BITPOS (13)\r
+#define GIRQ21_VBAT_VCI_IN3_BITPOS (14)\r
+#define GIRQ21_VBAT_VCI_IN4_BITPOS (15)\r
+#define GIRQ21_VBAT_VCI_IN5_BITPOS (16)\r
+#define GIRQ21_VBAT_VCI_IN6_BITPOS (17)\r
+#define GIRQ21_PS2_0A_WK_BITPOS (18)\r
+#define GIRQ21_PS2_0B_WK_BITPOS (19)\r
+#define GIRQ21_PS2_1A_WK_BITPOS (20)\r
+#define GIRQ21_PS2_1B_WK_BITPOS (21)\r
+#define GIRQ21_PS2_2_WK_BITPOS (22)\r
+#define GIRQ21_ENVMON_BITPOS (24)\r
+#define GIRQ21_KSC_INT_BITPOS (25)\r
+\r
+//\r
+#define GIRQ21_MASK (0x37FFFFFul)\r
+#define GIRQ21_WAKE_CAPABLE_MASK (0x37FFFFFul)\r
+//\r
+\r
+// GIRQ22 Bit Positions \r
+#define GIRQ22_LPC_WAKE_ONLY_BITPOS (0)\r
+#define GIRQ22_SMB0_WAKE_ONLY_BITPOS (1)\r
+#define GIRQ22_SMB1_WAKE_ONLY_BITPOS (2)\r
+#define GIRQ22_SMB2_WAKE_ONLY_BITPOS (3)\r
+#define GIRQ22_SMB3_WAKE_ONLY_BITPOS (4)\r
+#define GIRQ22_ESPI_WAKE_ONLY_BITPOS (9)\r
+\r
+#define GIRQ22_MASK (0x021Ful)\r
+#define GIRQ22_WAKE_CAPABLE_MASK (0x021Ful)\r
+\r
+// GIRQ23 Bit Positions \r
+#define GIRQ23_TMR0_BITPOS (0)\r
+#define GIRQ23_TMR1_BITPOS (1)\r
+#define GIRQ23_TMR2_BITPOS (2)\r
+#define GIRQ23_TMR3_BITPOS (3)\r
+#define GIRQ23_TMR4_BITPOS (4)\r
+#define GIRQ23_TMR5_BITPOS (5)\r
+#define GIRQ23_CTIMER0_BITPOS (6)\r
+#define GIRQ23_CTIMER1_BITPOS (7)\r
+#define GIRQ23_CTIMER2_BITPOS (8)\r
+#define GIRQ23_CTIMER3_BITPOS (9)\r
+#define GIRQ23_CAP_TIMER_BITPOS (10)\r
+#define GIRQ23_CCTIMER0_BITPOS (11)\r
+#define GIRQ23_CCTIMER1_BITPOS (12)\r
+#define GIRQ23_CCTIMER2_BITPOS (13)\r
+#define GIRQ23_CCTIMER3_BITPOS (14)\r
+#define GIRQ23_CCTIMER4_BITPOS (15)\r
+#define GIRQ23_CCTIMER5_BITPOS (16)\r
+#define GIRQ23_CCTIMER6_BITPOS (17)\r
+#define GIRQ23_CCTIMER7_BITPOS (18)\r
+\r
+//\r
+#define GIRQ23_MASK (0x07FFFFul)\r
+#define GIRQ23_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ24 Bit Positions\r
+#define GIRQ24_ESPI_VW00_SRC0_BITPOS (0)\r
+#define GIRQ24_ESPI_VW00_SRC1_BITPOS (1)\r
+#define GIRQ24_ESPI_VW00_SRC2_BITPOS (2)\r
+#define GIRQ24_ESPI_VW00_SRC3_BITPOS (3)\r
+#define GIRQ24_ESPI_VW01_SRC0_BITPOS (4)\r
+#define GIRQ24_ESPI_VW01_SRC1_BITPOS (5)\r
+#define GIRQ24_ESPI_VW01_SRC2_BITPOS (6)\r
+#define GIRQ24_ESPI_VW01_SRC3_BITPOS (7)\r
+#define GIRQ24_ESPI_VW02_SRC0_BITPOS (8)\r
+#define GIRQ24_ESPI_VW02_SRC1_BITPOS (9)\r
+#define GIRQ24_ESPI_VW02_SRC2_BITPOS (10)\r
+#define GIRQ24_ESPI_VW02_SRC3_BITPOS (11)\r
+#define GIRQ24_ESPI_VW03_SRC0_BITPOS (12)\r
+#define GIRQ24_ESPI_VW03_SRC1_BITPOS (13)\r
+#define GIRQ24_ESPI_VW03_SRC2_BITPOS (14)\r
+#define GIRQ24_ESPI_VW03_SRC3_BITPOS (15)\r
+#define GIRQ24_ESPI_VW04_SRC0_BITPOS (16)\r
+#define GIRQ24_ESPI_VW04_SRC1_BITPOS (17)\r
+#define GIRQ24_ESPI_VW04_SRC2_BITPOS (18)\r
+#define GIRQ24_ESPI_VW04_SRC3_BITPOS (19)\r
+#define GIRQ24_ESPI_VW05_SRC0_BITPOS (20)\r
+#define GIRQ24_ESPI_VW05_SRC1_BITPOS (21)\r
+#define GIRQ24_ESPI_VW05_SRC2_BITPOS (22)\r
+#define GIRQ24_ESPI_VW05_SRC3_BITPOS (23)\r
+#define GIRQ24_ESPI_VW06_SRC0_BITPOS (24)\r
+#define GIRQ24_ESPI_VW06_SRC1_BITPOS (25)\r
+#define GIRQ24_ESPI_VW06_SRC2_BITPOS (26)\r
+#define GIRQ24_ESPI_VW06_SRC3_BITPOS (27)\r
+\r
+//\r
+#define GIRQ24_MASK (0x0FFFFFFFul)\r
+#define GIRQ24_WAKE_CAPABLE_MASK (0x0FFFFFFFul)\r
+//\r
+\r
+// GIRQ25 Bit Positions\r
+#define GIRQ25_ESPI_VW07_SRC0_BITPOS (0)\r
+#define GIRQ25_ESPI_VW07_SRC1_BITPOS (1)\r
+#define GIRQ25_ESPI_VW07_SRC2_BITPOS (2)\r
+#define GIRQ25_ESPI_VW07_SRC3_BITPOS (3)\r
+#define GIRQ25_ESPI_VW08_SRC0_BITPOS (4)\r
+#define GIRQ25_ESPI_VW08_SRC1_BITPOS (5)\r
+#define GIRQ25_ESPI_VW08_SRC2_BITPOS (6)\r
+#define GIRQ25_ESPI_VW08_SRC3_BITPOS (7)\r
+#define GIRQ25_ESPI_VW09_SRC0_BITPOS (8)\r
+#define GIRQ25_ESPI_VW09_SRC1_BITPOS (9)\r
+#define GIRQ25_ESPI_VW09_SRC2_BITPOS (10)\r
+#define GIRQ25_ESPI_VW09_SRC3_BITPOS (11)\r
+#define GIRQ25_ESPI_VW10_SRC0_BITPOS (12)\r
+#define GIRQ25_ESPI_VW10_SRC1_BITPOS (13)\r
+#define GIRQ25_ESPI_VW10_SRC2_BITPOS (14)\r
+#define GIRQ25_ESPI_VW10_SRC3_BITPOS (15)\r
+\r
+//\r
+#define GIRQ25_MASK (0x0FFFFul)\r
+#define GIRQ25_WAKE_CAPABLE_MASK (0x0FFFFul)\r
+//\r
+\r
+// GIRQ26 bit positions\r
+#define GIRQ26_GPIO240_BITPOS (0)\r
+#define GIRQ26_GPIO241_BITPOS (1)\r
+#define GIRQ26_GPIO242_BITPOS (2)\r
+#define GIRQ26_GPIO243_BITPOS (3)\r
+#define GIRQ26_GPIO244_BITPOS (4)\r
+#define GIRQ26_GPIO245_BITPOS (5)\r
+#define GIRQ26_GPIO246_BITPOS (6)\r
+#define GIRQ26_GPIO247_BITPOS (7)\r
+\r
+#define GIRQ26_GPIO250_BITPOS (8)\r
+#define GIRQ26_GPIO251_BITPOS (9)\r
+#define GIRQ26_GPIO252_BITPOS (10)\r
+#define GIRQ26_GPIO253_BITPOS (11)\r
+#define GIRQ26_GPIO254_BITPOS (12)\r
+#define GIRQ26_GPIO255_BITPOS (13)\r
+#define GIRQ26_GPIO256_BITPOS (14)\r
+#define GIRQ26_GPIO257_BITPOS (15)\r
+\r
+#define GIRQ26_GPIO260_BITPOS (16)\r
+#define GIRQ26_GPIO261_BITPOS (17)\r
+#define GIRQ26_GPIO262_BITPOS (18)\r
+#define GIRQ26_GPIO263_BITPOS (19)\r
+#define GIRQ26_GPIO264_BITPOS (20)\r
+#define GIRQ26_GPIO265_BITPOS (21)\r
+#define GIRQ26_GPIO266_BITPOS (22)\r
+#define GIRQ26_GPIO267_BITPOS (23)\r
+\r
+#define GIRQ26_GPIO270_BITPOS (24)\r
+#define GIRQ26_GPIO271_BITPOS (25)\r
+#define GIRQ26_GPIO272_BITPOS (26)\r
+#define GIRQ26_GPIO273_BITPOS (27)\r
+#define GIRQ26_GPIO274_BITPOS (28)\r
+#define GIRQ26_GPIO275_BITPOS (29)\r
+#define GIRQ26_GPIO276_BITPOS (30)\r
+\r
+#define GIRQ26_MASK (0x7FFFFFFFul)\r
+#define GIRQ26_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC,ECIA Routing Policy for Direct Mode */\r
+/* ------------------------------------------------------------------------------- */\r
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
+ * Configuration:\r
+ * 1. Always set ECS Interrupt Direct enable bit. \r
+ * 2. If GIRQn aggregated set Block Enable bit.\r
+ * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
+ * Switching issues:\r
+ * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
+ * Also requires set/clear of individual NVIC Enables.\r
+ * \r
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
+ * if any interrupt is configured as direct or aggregated\r
+*/\r
+\r
+/** Initialize EC Interrupt Aggregator\r
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
+ * This parameter is only applicable in direct mode.\r
+ * @note All GPIO's and wake capable sources are always \r
+ * aggregated! GPIO's interrupts will still work in direct mode.\r
+ * Block wakes are not be routed to the processor in direct \r
+ * mode. \r
+ * Note2: This function disables and enables global interrupt \r
+ */\r
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask);\r
+\r
+/** Set interrupt routing mode to aggregated or direct. \r
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
+ * @note In direct mode, one could enable certain GIRQs as aggregated using \r
+ * p_interrupt_ecia_block_enable_set function\r
+ */\r
+void interrupt_mode_set(uint8_t mode);\r
+\r
+/** Clears all individual interrupts Enables and Source in ECIA,\r
+ * and Clears all NVIC external enables and pending bits \r
+ */\r
+void interrupt_reset(void);\r
+\r
+/** Enables interrupt for a device \r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_enable(uint32_t dev_iroute);\r
+\r
+/** Disables interrupt for a device\r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_disable(uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* ECIA APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear Source in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ */\r
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);\r
+\r
+/** Get the Source bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);\r
+\r
+/** Get the Result bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if result bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
+ * NVIC corresponding to the aggregated GIRQ \r
+ */\r
+\r
+/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
+ * @note Recommended to use interrupt_device_enable, interrupt_device_disable\r
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
+ */\r
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);\r
+\r
+/** Set NVIC priority for specified peripheral interrupt source\r
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
+ * @param nvic_pri - NVIC Priority\r
+ * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt \r
+ * sources in the GIRQ. \r
+ * 2. This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);\r
+\r
+/** Return NVIC priority for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint32_t NVIC priority \r
+ */\r
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);\r
+\r
+/** Return NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
+ * \r
+ */\r
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);\r
+\r
+/** Set NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ */\r
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);\r
+\r
+/** Clears NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *\r
+ * and Status Register */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable specified GIRQ in ECIA block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+ void p_interrupt_ecia_block_enable_set(uint8_t girq_id);\r
+ \r
+ /** Enable GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);\r
+\r
+/** Check if specified GIRQ block enabled or not\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
+ */\r
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);\r
+\r
+/** Set all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_set(void);\r
+\r
+/** Clear specified GIRQ in ECIA Block \r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);\r
+\r
+/** Clear GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);\r
+\r
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_clr(void);\r
+ \r
+ /** Get status of GIRQ in ECIA Block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return 0 if status bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);\r
+\r
+/** Reads the Block IRQ Vector Register\r
+ * @return 32-bit value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void);\r
+\r
+/* ---------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *\r
+ * and Enable Registers */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/** Clear specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Enable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Disable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the status of the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the result bit of the interrupt in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Operations on all GIRQs */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear all aggregator GIRQn status registers */\r
+void p_interrupt_ecia_girqs_source_reset(void);\r
+\r
+/** Clear all aggregator GIRQn enables */\r
+ void p_interrupt_ecia_girqs_enable_reset(void);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to set interrupt control */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Set interrupt control \r
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+ void p_interrupt_control_set(uint8_t nvic_en_flag);\r
+ \r
+ /** Read interrupt control \r
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+uint8_t p_interrupt_control_get(void);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - NVIC */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
+ * @param nvic_num : NVIC number (see enum IRQn_Type)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ\r
+ * @note Application should perform this operation\r
+ */\r
+ void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);\r
+ \r
+ /** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
+void p_interrupt_nvic_extEnables_clr(void);\r
+\r
+/** Clear all NVIC external enables and pending bits */\r
+void p_interrupt_nvic_enpend_clr(void);\r
+\r
+/** Set NVIC external priorities to POR value */\r
+void p_interrupt_nvic_priorities_default_set(void);\r
+\r
+/** Set NVIC external priorities to specified priority (0 - 7)\r
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
+ * @note NVIC highest priority is the value 0, lowest is all 1's.\r
+ * Each external interrupt has an 8-bit register and the priority \r
+ * is left justified in the registers. MECxxx implements 8 priority \r
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
+ */\r
+void p_interrupt_nvic_priorities_set(uint8_t new_pri);\r
+\r
+#endif // #ifndef _INTERRUPT_H\r
+/* end interrupt.h */\r
+/** @}\r
+ */\r
+\r
+\r
+\r
projects / freertos / blobdiff