/**************************************************************************//**\r
* @file core_cmInstr.h\r
* @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V3.20\r
- * @date 05. March 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.20\r
+ * @date 02. July 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
#ifndef __CORE_CMINSTR_H\r
#define __CORE_CMINSTR_H\r
\r
@{\r
*/\r
\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constrant "l"\r
- * Otherwise, use general registers, specified by constrant "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32 - op2)); \r
-}\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/\r
+ #include <cmsis_armcc.h>\r
\r
-#endif /* (__CORTEX_M >= 0x03) */\r
+#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/\r
+ #include <cmsis_armcc_V6.h>\r
\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/\r
+ #include <cmsis_gcc.h>\r
\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/\r
+ #include <cmsis_iar.h>\r
\r
+#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/\r
+ #include <cmsis_ccs.h>\r
\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/\r
+ #include <cmsis_csm.h>\r
\r
#endif\r
\r
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