/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
static bool is_A_Module(uint32_t module)
{
- if (module == EUSCI_A0_MODULE || module == EUSCI_A1_MODULE
-#ifdef EUSCI_A2_MODULE
- || module == EUSCI_A2_MODULE
+ if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
+#ifdef EUSCI_A2_BASE
+ || module == EUSCI_A2_BASE
#endif
-#ifdef EUSCI_A3_MODULE
- || module == EUSCI_A3_MODULE
+#ifdef EUSCI_A3_BASE
+ || module == EUSCI_A3_BASE
#endif
)
return true;
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
+ /* Returning false if we are not divisible */
+ if((config->clockSourceFrequency
+ % config->desiredSpiClock) != 0)
+ {
+ return false;
+ }
+
if (is_A_Module(moduleInstance))
{
ASSERT(
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
-
+
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
- * UCMST = Master mode
- * UCSYNC = Synchronous mode
+ * EUSCI_A_CTLW0_MST = Master mode
+ * EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
- + UCMODE_3 + UCSYNC))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
- + UCMST + UCSYNC + config->spiMode);
-
- EUSCI_A_CMSIS(moduleInstance)->rBRW =
+ + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
+
+ EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
- EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
+ EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
return true;
} else
== config->spiMode));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
- * UCMST = Master mode
- * UCSYNC = Synchronous mode
+ * EUSCI_A_CTLW0_MST = Master mode
+ * EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
- + UCMODE_3 + UCSYNC))
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
- + UCMST + UCSYNC + config->spiMode);
+ + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
- EUSCI_B_CMSIS(moduleInstance)->rBRW =
+ EUSCI_B_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
== config->spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
- + config->msbFirst + UCSYNC + config->spiMode);
+ + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
} else
== config->spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
- + config->msbFirst + UCSYNC + config->spiMode);
+ + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
}
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
- & HWREG16(moduleInstance + OFS_UCA0IE);
+ & EUSCI_A_CMSIS(moduleInstance)->IE;
+
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
- & HWREG16(moduleInstance + OFS_UCB0IE);
+ & EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
#endif
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
#endif
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
|| (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~UCSTEM) | select4PinFunctionality;
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+ EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
-//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
- | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
+ | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
-//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
== clockPhase));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
//*****************************************************************************
void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
- EUSCI_B_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+ EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
//*****************************************************************************
uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
{
- return EUSCI_B_CMSIS(baseAddress)->rRXBUF.r;
+ return EUSCI_B_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIE.r |= mask;
+ EUSCI_B_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask;
+ EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask;
+ return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask;
+ EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
void EUSCI_B_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
void EUSCI_B_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
//*****************************************************************************
uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCB0RXBUF;
+ return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
}
//*****************************************************************************
//*****************************************************************************
uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCB0TXBUF;
+ return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
}
//*****************************************************************************
bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
- return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+ return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}
//*****************************************************************************
|| (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~UCSTEM) | select4PinFunctionality;
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+ EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
-//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
- | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
+ | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
-//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
== clockPhase));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
//*****************************************************************************
void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
- EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+ EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
//*****************************************************************************
uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
{
- return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
+ return EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIE.r |= mask;
+ EUSCI_A_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
+ EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
+ return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
+ EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
void EUSCI_A_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
void EUSCI_A_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
//*****************************************************************************
uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCA0RXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
//*****************************************************************************
uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCA0TXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
}
//*****************************************************************************
bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
- return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+ return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}
projects / freertos / blobdiff