/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
/* Disable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/* Clock source select */
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_3)
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
| config->selectClockSource;
/* MSB, LSB select */
if (config->msborLsbFirst)
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
else
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
if (config->numberofStopBits)
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
else
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
/* Parity */
switch (config->parity)
{
case EUSCI_A_UART_NO_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
break;
case EUSCI_A_UART_ODD_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
break;
case EUSCI_A_UART_EVEN_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
break;
}
/* BaudRate Control Register */
- EUSCI_A_CMSIS(moduleInstance)->rBRW = config->clockPrescalar;
- EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = ((config->secondModReg << 8)
+ EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
+ EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
+ (config->firstModReg << 4) + config->overSampling);
/* Asynchronous mode & 8 bit character select & clear mode */
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSYNC | UC7BIT | UCMODE_3 | UCRXEIE | UCBRKIE | UCDORM
- | UCTXADDR | UCTXBRK)) | config->uartMode;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
+ | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
return retVal;
}
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCRXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
- return EUSCI_A_CMSIS(moduleInstance)->rRXBUF.r;
+ return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
void UART_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
void UART_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
+ EUSCI_A_UART_ADDRESS_RECEIVED
+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
- return EUSCI_A_CMSIS(moduleInstance)->rSTATW.r & mask;
+ return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
}
void UART_setDormant(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
}
void UART_resetDormant(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
}
void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
{
/* Set UCTXADDR bit */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXADDR_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
/* Place next byte to be sent into the transmit buffer */
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitAddress;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
}
void UART_transmitBreak(uint32_t moduleInstance)
{
/* Set UCTXADDR bit */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXBRK_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
/* If current mode is automatic baud-rate detection */
if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
- == (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+ == (EUSCI_A_CMSIS(moduleInstance)->CTLW0
& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r =
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF =
EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
else
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = DEFAULT_SYNC;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
}
uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCA0RXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCA0TXBUF;
+ return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r & ~(UCGLIT_M))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
| deglitchTime;
}
void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
- uint8_t locMask;
+ uint_fast8_t locMask;
ASSERT(
!(mask
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rIE.r |= locMask;
+ EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r |= locMask;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
}
void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
- uint8_t locMask;
+ uint_fast8_t locMask;
ASSERT(
!(mask
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rIE.r &= ~locMask;
+ EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r &= ~locMask;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
}
uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
- return EUSCI_A_CMSIS(moduleInstance)->rIFG.r & mask;
+ return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
}
uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
- uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->rIE.r;
+ uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
}
- intEnabled = EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r;
+ intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
//Clear the UART interrupt source.
- EUSCI_A_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
+ EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
}
void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
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