DCD Reset_Handler ; Reset Handler\r
DCD NMI_Handler ; NMI Handler\r
DCD HardFault_Handler ; Hard Fault Handler\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
DCD 0 ; Reserved\r
DCD 0 ; Reserved\r
DCD 0 ; Reserved\r
DCD 0 ; Reserved\r
DCD SVC_Handler ; SVCall Handler\r
- DCD 0 ; Reserved\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
DCD 0 ; Reserved\r
DCD PendSV_Handler ; PendSV Handler\r
DCD SysTick_Handler ; SysTick Handler\r
\r
; External Interrupts\r
- DCD IntDefault_Handler ; PSS ISR\r
- DCD IntDefault_Handler ; CS ISR \r
- DCD IntDefault_Handler ; PCM ISR\r
- DCD IntDefault_Handler ; WDT ISR\r
- DCD IntDefault_Handler ; FPU ISR\r
- DCD IntDefault_Handler ; FLCTL ISR\r
- DCD IntDefault_Handler ; COMP0 ISR\r
- DCD IntDefault_Handler ; COMP1 ISR\r
- DCD IntDefault_Handler ; TA0_0 ISR \r
- DCD IntDefault_Handler ; TA0_N ISR\r
- DCD IntDefault_Handler ; TA1_0 ISR\r
- DCD IntDefault_Handler ; TA1_N ISR\r
- DCD IntDefault_Handler ; TA2_0 ISR\r
- DCD IntDefault_Handler ; TA2_N ISR\r
- DCD IntDefault_Handler ; TA3_0 ISR\r
- DCD IntDefault_Handler ; TA3_N ISR\r
+ DCD PSS_IRQHandler ; 0: PSS Interrupt\r
+ DCD CS_IRQHandler ; 1: CS Interrupt\r
+ DCD PCM_IRQHandler ; 2: PCM Interrupt\r
+ DCD WDT_A_IRQHandler ; 3: WDT_A Interrupt\r
+ DCD FPU_IRQHandler ; 4: FPU Interrupt\r
+ DCD FLCTL_IRQHandler ; 5: FLCTL Interrupt\r
+ DCD COMP_E0_IRQHandler ; 6: COMP_E0 Interrupt\r
+ DCD COMP_E1_IRQHandler ; 7: COMP_E1 Interrupt\r
+ DCD TA0_0_IRQHandler ; 8: TA0_0 Interrupt\r
+ DCD TA0_N_IRQHandler ; 9: TA0_N Interrupt\r
+ DCD TA1_0_IRQHandler ; 10: TA1_0 Interrupt\r
+ DCD TA1_N_IRQHandler ; 11: TA1_N Interrupt\r
+ DCD TA2_0_IRQHandler ; 12: TA2_0 Interrupt\r
+ DCD TA2_N_IRQHandler ; 13: TA2_N Interrupt\r
+ DCD TA3_0_IRQHandler ; 14: TA3_0 Interrupt\r
+ DCD TA3_N_IRQHandler ; 15: TA3_N Interrupt\r
DCD vUART_Handler ; EUSCIA0 ISR\r
- DCD IntDefault_Handler ; EUSCIA1 ISR\r
- DCD IntDefault_Handler ; EUSCIA2 ISR\r
- DCD IntDefault_Handler ; EUSCIA3 ISR\r
- DCD IntDefault_Handler ; EUSCIB0 ISR\r
- DCD IntDefault_Handler ; EUSCIB1 ISR\r
- DCD IntDefault_Handler ; EUSCIB2 ISR\r
- DCD IntDefault_Handler ; EUSCIB3 ISR\r
- DCD IntDefault_Handler ; ADC12 ISR\r
+ DCD EUSCIA1_IRQHandler ; 17: EUSCIA1 Interrupt\r
+ DCD EUSCIA2_IRQHandler ; 18: EUSCIA2 Interrupt\r
+ DCD EUSCIA3_IRQHandler ; 19: EUSCIA3 Interrupt\r
+ DCD EUSCIB0_IRQHandler ; 20: EUSCIB0 Interrupt\r
+ DCD EUSCIB1_IRQHandler ; 21: EUSCIB1 Interrupt\r
+ DCD EUSCIB2_IRQHandler ; 22: EUSCIB2 Interrupt\r
+ DCD EUSCIB3_IRQHandler ; 23: EUSCIB3 Interrupt\r
+ DCD ADC14_IRQHandler ; 24: ADC14 Interrupt\r
DCD vT32_0_Handler ; T32_INT1 ISR\r
DCD vT32_1_Handler ; T32_INT2 ISR\r
- DCD IntDefault_Handler ; T32_INTC ISR\r
- DCD IntDefault_Handler ; AES ISR\r
- DCD IntDefault_Handler ; RTC ISR\r
- DCD IntDefault_Handler ; DMA_ERR ISR\r
- DCD IntDefault_Handler ; DMA_INT3 ISR\r
- DCD IntDefault_Handler ; DMA_INT2 ISR\r
- DCD IntDefault_Handler ; DMA_INT1 ISR\r
- DCD IntDefault_Handler ; DMA_INT0 ISR\r
- DCD IntDefault_Handler ; PORT1 ISR\r
- DCD IntDefault_Handler ; PORT2 ISR\r
- DCD IntDefault_Handler ; PORT3 ISR\r
- DCD IntDefault_Handler ; PORT4 ISR\r
- DCD IntDefault_Handler ; PORT5 ISR\r
- DCD IntDefault_Handler ; PORT6 ISR\r
- DCD IntDefault_Handler ; Reserved 41\r
- DCD IntDefault_Handler ; Reserved 42\r
- DCD IntDefault_Handler ; Reserved 43\r
- DCD IntDefault_Handler ; Reserved 44\r
- DCD IntDefault_Handler ; Reserved 45\r
- DCD IntDefault_Handler ; Reserved 46\r
- DCD IntDefault_Handler ; Reserved 47\r
- DCD IntDefault_Handler ; Reserved 48\r
- DCD IntDefault_Handler ; Reserved 49\r
- DCD IntDefault_Handler ; Reserved 50\r
- DCD IntDefault_Handler ; Reserved 51\r
- DCD IntDefault_Handler ; Reserved 52\r
- DCD IntDefault_Handler ; Reserved 53\r
- DCD IntDefault_Handler ; Reserved 54\r
- DCD IntDefault_Handler ; Reserved 55\r
- DCD IntDefault_Handler ; Reserved 56\r
- DCD IntDefault_Handler ; Reserved 57\r
- DCD IntDefault_Handler ; Reserved 58\r
- DCD IntDefault_Handler ; Reserved 59\r
- DCD IntDefault_Handler ; Reserved 60\r
- DCD IntDefault_Handler ; Reserved 61\r
- DCD IntDefault_Handler ; Reserved 62\r
- DCD IntDefault_Handler ; Reserved 63\r
- DCD IntDefault_Handler ; Reserved 64\r
+ DCD T32_INTC_IRQHandler ; 27: T32_INTC Interrupt\r
+ DCD AES256_IRQHandler ; 28: AES256 Interrupt\r
+ DCD RTC_C_IRQHandler ; 29: RTC_C Interrupt\r
+ DCD DMA_ERR_IRQHandler ; 30: DMA_ERR Interrupt\r
+ DCD DMA_INT3_IRQHandler ; 31: DMA_INT3 Interrupt\r
+ DCD DMA_INT2_IRQHandler ; 32: DMA_INT2 Interrupt\r
+ DCD DMA_INT1_IRQHandler ; 33: DMA_INT1 Interrupt\r
+ DCD DMA_INT0_IRQHandler ; 34: DMA_INT0 Interrupt\r
+ DCD PORT1_IRQHandler ; 35: PORT1 Interrupt\r
+ DCD PORT2_IRQHandler ; 36: PORT2 Interrupt\r
+ DCD PORT3_IRQHandler ; 37: PORT3 Interrupt\r
+ DCD PORT4_IRQHandler ; 38: PORT4 Interrupt\r
+ DCD PORT5_IRQHandler ; 39: PORT5 Interrupt\r
+ DCD PORT6_IRQHandler ; 40: PORT6 Interrupt\r
+ DCD 0 ; 41: Reserved\r
+ DCD 0 ; 42: Reserved\r
+ DCD 0 ; 43: Reserved\r
+ DCD 0 ; 44: Reserved\r
+ DCD 0 ; 45: Reserved\r
+ DCD 0 ; 46: Reserved\r
+ DCD 0 ; 47: Reserved\r
+ DCD 0 ; 48: Reserved\r
+ DCD 0 ; 49: Reserved\r
+ DCD 0 ; 50: Reserved\r
+ DCD 0 ; 51: Reserved\r
+ DCD 0 ; 52: Reserved\r
+ DCD 0 ; 53: Reserved\r
+ DCD 0 ; 54: Reserved\r
+ DCD 0 ; 55: Reserved\r
+ DCD 0 ; 56: Reserved\r
+ DCD 0 ; 57: Reserved\r
+ DCD 0 ; 58: Reserved\r
+ DCD 0 ; 59: Reserved\r
+ DCD 0 ; 60: Reserved\r
+ DCD 0 ; 61: Reserved\r
+ DCD 0 ; 62: Reserved\r
+ DCD 0 ; 63: Reserved\r
+ DCD 0 ; 64: Reserved\r
__Vectors_End\r
\r
__Vectors_Size EQU __Vectors_End - __Vectors\r
EXPORT HardFault_Handler [WEAK]\r
B .\r
ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
SVC_Handler PROC\r
EXPORT SVC_Handler [WEAK]\r
B .\r
ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
PendSV_Handler PROC\r
EXPORT PendSV_Handler [WEAK]\r
B .\r
EXPORT SysTick_Handler [WEAK]\r
B .\r
ENDP\r
-IntDefault_Handler PROC\r
- EXPORT IntDefault_Handler [WEAK]\r
+\r
+Default_Handler PROC\r
+ EXPORT PSS_IRQHandler [WEAK]\r
+ EXPORT CS_IRQHandler [WEAK]\r
+ EXPORT PCM_IRQHandler [WEAK]\r
+ EXPORT WDT_A_IRQHandler [WEAK]\r
+ EXPORT FPU_IRQHandler [WEAK]\r
+ EXPORT FLCTL_IRQHandler [WEAK]\r
+ EXPORT COMP_E0_IRQHandler [WEAK]\r
+ EXPORT COMP_E1_IRQHandler [WEAK]\r
+ EXPORT TA0_0_IRQHandler [WEAK]\r
+ EXPORT TA0_N_IRQHandler [WEAK]\r
+ EXPORT TA1_0_IRQHandler [WEAK]\r
+ EXPORT TA1_N_IRQHandler [WEAK]\r
+ EXPORT TA2_0_IRQHandler [WEAK]\r
+ EXPORT TA2_N_IRQHandler [WEAK]\r
+ EXPORT TA3_0_IRQHandler [WEAK]\r
+ EXPORT TA3_N_IRQHandler [WEAK]\r
+ EXPORT EUSCIA0_IRQHandler [WEAK]\r
+ EXPORT EUSCIA1_IRQHandler [WEAK]\r
+ EXPORT EUSCIA2_IRQHandler [WEAK]\r
+ EXPORT EUSCIA3_IRQHandler [WEAK]\r
+ EXPORT EUSCIB0_IRQHandler [WEAK]\r
+ EXPORT EUSCIB1_IRQHandler [WEAK]\r
+ EXPORT EUSCIB2_IRQHandler [WEAK]\r
+ EXPORT EUSCIB3_IRQHandler [WEAK]\r
+ EXPORT ADC14_IRQHandler [WEAK]\r
+ EXPORT T32_INT1_IRQHandler [WEAK]\r
+ EXPORT T32_INT2_IRQHandler [WEAK]\r
+ EXPORT T32_INTC_IRQHandler [WEAK]\r
+ EXPORT AES256_IRQHandler [WEAK]\r
+ EXPORT RTC_C_IRQHandler [WEAK]\r
+ EXPORT DMA_ERR_IRQHandler [WEAK]\r
+ EXPORT DMA_INT3_IRQHandler [WEAK]\r
+ EXPORT DMA_INT2_IRQHandler [WEAK]\r
+ EXPORT DMA_INT1_IRQHandler [WEAK]\r
+ EXPORT DMA_INT0_IRQHandler [WEAK]\r
+ EXPORT PORT1_IRQHandler [WEAK]\r
+ EXPORT PORT2_IRQHandler [WEAK]\r
+ EXPORT PORT3_IRQHandler [WEAK]\r
+ EXPORT PORT4_IRQHandler [WEAK]\r
+ EXPORT PORT5_IRQHandler [WEAK]\r
+ EXPORT PORT6_IRQHandler [WEAK]\r
+\r
+PSS_IRQHandler\r
+CS_IRQHandler\r
+PCM_IRQHandler\r
+WDT_A_IRQHandler\r
+FPU_IRQHandler\r
+FLCTL_IRQHandler\r
+COMP_E0_IRQHandler\r
+COMP_E1_IRQHandler\r
+TA0_0_IRQHandler\r
+TA0_N_IRQHandler\r
+TA1_0_IRQHandler\r
+TA1_N_IRQHandler\r
+TA2_0_IRQHandler\r
+TA2_N_IRQHandler\r
+TA3_0_IRQHandler\r
+TA3_N_IRQHandler\r
+EUSCIA0_IRQHandler\r
+EUSCIA1_IRQHandler\r
+EUSCIA2_IRQHandler\r
+EUSCIA3_IRQHandler\r
+EUSCIB0_IRQHandler\r
+EUSCIB1_IRQHandler\r
+EUSCIB2_IRQHandler\r
+EUSCIB3_IRQHandler\r
+ADC14_IRQHandler\r
+T32_INT1_IRQHandler\r
+T32_INT2_IRQHandler\r
+T32_INTC_IRQHandler\r
+AES256_IRQHandler\r
+RTC_C_IRQHandler\r
+DMA_ERR_IRQHandler\r
+DMA_INT3_IRQHandler\r
+DMA_INT2_IRQHandler\r
+DMA_INT1_IRQHandler\r
+DMA_INT0_IRQHandler\r
+PORT1_IRQHandler\r
+PORT2_IRQHandler\r
+PORT3_IRQHandler\r
+PORT4_IRQHandler\r
+PORT5_IRQHandler\r
+PORT6_IRQHandler\r
B .\r
ENDP\r
\r
ALIGN\r
\r
- \r
+\r
; User Initial Stack & Heap\r
\r
IF :DEF:__MICROLIB\r
\r
IMPORT __use_two_region_memory\r
EXPORT __user_initial_stackheap\r
-__user_initial_stackheap\r
\r
+__user_initial_stackheap PROC\r
LDR R0, = Heap_Mem\r
LDR R1, =(Stack_Mem + Stack_Size)\r
LDR R2, = (Heap_Mem + Heap_Size)\r
LDR R3, = Stack_Mem\r
BX LR\r
+ ENDP\r
\r
ALIGN\r
\r
projects / freertos / blobdiff