Kernel changes:

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAMV71_Xplained / libchip_samv7 / include / samv7 / instance / instance_aes.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_aes.h
new file mode 100644 (file)
index 0000000..63fdb02
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_aes.h
@@ -0,0 +1,72 @@
+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_AES_INSTANCE_\r
+#define _SAM_AES_INSTANCE_\r
+\r
+/* ========== Register definition for AES peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_AES_CR                       (0x4006C000U) /**< \brief (AES) Control Register */\r
+  #define REG_AES_MR                       (0x4006C004U) /**< \brief (AES) Mode Register */\r
+  #define REG_AES_IER                      (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */\r
+  #define REG_AES_IDR                      (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */\r
+  #define REG_AES_IMR                      (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */\r
+  #define REG_AES_ISR                      (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */\r
+  #define REG_AES_KEYWR                    (0x4006C020U) /**< \brief (AES) Key Word Register */\r
+  #define REG_AES_IDATAR                   (0x4006C040U) /**< \brief (AES) Input Data Register */\r
+  #define REG_AES_ODATAR                   (0x4006C050U) /**< \brief (AES) Output Data Register */\r
+  #define REG_AES_IVR                      (0x4006C060U) /**< \brief (AES) Initialization Vector Register */\r
+  #define REG_AES_AADLENR                  (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */\r
+  #define REG_AES_CLENR                    (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */\r
+  #define REG_AES_GHASHR                   (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */\r
+  #define REG_AES_TAGR                     (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */\r
+  #define REG_AES_CTRR                     (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */\r
+  #define REG_AES_GCMHR                    (0x4006C09CU) /**< \brief (AES) GCM H World Register */\r
+  #define REG_AES_VERSION                  (0x4006C0FCU) /**< \brief (AES) Version Register */\r
+#else\r
+  #define REG_AES_CR      (*(__O  uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */\r
+  #define REG_AES_MR      (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */\r
+  #define REG_AES_IER     (*(__O  uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */\r
+  #define REG_AES_IDR     (*(__O  uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */\r
+  #define REG_AES_IMR     (*(__I  uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */\r
+  #define REG_AES_ISR     (*(__I  uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */\r
+  #define REG_AES_KEYWR   (*(__O  uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */\r
+  #define REG_AES_IDATAR  (*(__O  uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */\r
+  #define REG_AES_ODATAR  (*(__I  uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */\r
+  #define REG_AES_IVR     (*(__O  uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */\r
+  #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */\r
+  #define REG_AES_CLENR   (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */\r
+  #define REG_AES_GHASHR  (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */\r
+  #define REG_AES_TAGR    (*(__I  uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */\r
+  #define REG_AES_CTRR    (*(__I  uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */\r
+  #define REG_AES_GCMHR   (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H World Register */\r
+  #define REG_AES_VERSION (*(__I  uint32_t*)0x4006C0FCU) /**< \brief (AES) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_AES_INSTANCE_ */\r