Kernel changes:

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAMV71_Xplained / libchip_samv7 / include / samv7 / instance / instance_qspi.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_qspi.h
new file mode 100644 (file)
index 0000000..49eaf09
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_qspi.h
@@ -0,0 +1,72 @@
+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_QSPI_INSTANCE_\r
+#define _SAM_QSPI_INSTANCE_\r
+\r
+/* ========== Register definition for QSPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_QSPI_CR                       (0x4007C000U) /**< \brief (QSPI) Control Register */\r
+  #define REG_QSPI_MR                       (0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+  #define REG_QSPI_RDR                      (0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+  #define REG_QSPI_TDR                      (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+  #define REG_QSPI_SR                       (0x4007C010U) /**< \brief (QSPI) Status Register */\r
+  #define REG_QSPI_IER                      (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+  #define REG_QSPI_IDR                      (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+  #define REG_QSPI_IMR                      (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+  #define REG_QSPI_SCR                      (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+  #define REG_QSPI_IAR                      (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+  #define REG_QSPI_ICR                      (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+  #define REG_QSPI_IFR                      (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+  #define REG_QSPI_SMR                      (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+  #define REG_QSPI_SKR                      (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+  #define REG_QSPI_WPMR                     (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+  #define REG_QSPI_WPSR                     (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+  #define REG_QSPI_VERSION                  (0x4007C0FCU) /**< \brief (QSPI) Version Register */\r
+#else\r
+  #define REG_QSPI_CR      (*(__O  uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */\r
+  #define REG_QSPI_MR      (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */\r
+  #define REG_QSPI_RDR     (*(__I  uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */\r
+  #define REG_QSPI_TDR     (*(__O  uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */\r
+  #define REG_QSPI_SR      (*(__I  uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */\r
+  #define REG_QSPI_IER     (*(__O  uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */\r
+  #define REG_QSPI_IDR     (*(__O  uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */\r
+  #define REG_QSPI_IMR     (*(__I  uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */\r
+  #define REG_QSPI_SCR     (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */\r
+  #define REG_QSPI_IAR     (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */\r
+  #define REG_QSPI_ICR     (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */\r
+  #define REG_QSPI_IFR     (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */\r
+  #define REG_QSPI_SMR     (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */\r
+  #define REG_QSPI_SKR     (*(__IO uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */\r
+  #define REG_QSPI_WPMR    (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */\r
+  #define REG_QSPI_WPSR    (*(__I  uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */\r
+  #define REG_QSPI_VERSION (*(__I  uint32_t*)0x4007C0FCU) /**< \brief (QSPI) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_QSPI_INSTANCE_ */\r