Kernel changes:

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAMV71_Xplained / libchip_samv7 / include / samv7 / instance / instance_sdramc.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_sdramc.h
new file mode 100644 (file)
index 0000000..edb0171
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_sdramc.h
@@ -0,0 +1,62 @@
+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SDRAMC_INSTANCE_\r
+#define _SAM_SDRAMC_INSTANCE_\r
+\r
+/* ========== Register definition for SDRAMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_SDRAMC_MR                       (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+  #define REG_SDRAMC_TR                       (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+  #define REG_SDRAMC_CR                       (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+  #define REG_SDRAMC_HSR                      (0x4008400CU) /**< \brief (SDRAMC) SDRAMC High Speed Register */\r
+  #define REG_SDRAMC_LPR                      (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+  #define REG_SDRAMC_IER                      (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+  #define REG_SDRAMC_IDR                      (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+  #define REG_SDRAMC_IMR                      (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+  #define REG_SDRAMC_ISR                      (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+  #define REG_SDRAMC_MDR                      (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+  #define REG_SDRAMC_CR1                      (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+  #define REG_SDRAMC_VERSION                  (0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */\r
+#else\r
+  #define REG_SDRAMC_MR      (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+  #define REG_SDRAMC_TR      (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+  #define REG_SDRAMC_CR      (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+  #define REG_SDRAMC_HSR     (*(__IO uint32_t*)0x4008400CU) /**< \brief (SDRAMC) SDRAMC High Speed Register */\r
+  #define REG_SDRAMC_LPR     (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+  #define REG_SDRAMC_IER     (*(__O  uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+  #define REG_SDRAMC_IDR     (*(__O  uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+  #define REG_SDRAMC_IMR     (*(__I  uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+  #define REG_SDRAMC_ISR     (*(__I  uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+  #define REG_SDRAMC_MDR     (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+  #define REG_SDRAMC_CR1     (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+  #define REG_SDRAMC_VERSION (*(__I  uint32_t*)0x400840FCU) /**< \brief (SDRAMC) SDRAMC Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SDRAMC_INSTANCE_ */\r