Kernel changes:

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAMV71_Xplained / libchip_samv7 / include / samv7 / instance / instance_ssc.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_ssc.h
new file mode 100644 (file)
index 0000000..cacb4e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained/libchip_samv7/include/samv7/instance/instance_ssc.h
@@ -0,0 +1,76 @@
+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2014, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAM_SSC_INSTANCE_\r
+#define _SAM_SSC_INSTANCE_\r
+\r
+/* ========== Register definition for SSC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+  #define REG_SSC_CR                       (0x40004000U) /**< \brief (SSC) Control Register */\r
+  #define REG_SSC_CMR                      (0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+  #define REG_SSC_RCMR                     (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+  #define REG_SSC_RFMR                     (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+  #define REG_SSC_TCMR                     (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+  #define REG_SSC_TFMR                     (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+  #define REG_SSC_RHR                      (0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+  #define REG_SSC_THR                      (0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+  #define REG_SSC_RSHR                     (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+  #define REG_SSC_TSHR                     (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+  #define REG_SSC_RC0R                     (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+  #define REG_SSC_RC1R                     (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+  #define REG_SSC_SR                       (0x40004040U) /**< \brief (SSC) Status Register */\r
+  #define REG_SSC_IER                      (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+  #define REG_SSC_IDR                      (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+  #define REG_SSC_IMR                      (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+  #define REG_SSC_WPMR                     (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+  #define REG_SSC_WPSR                     (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+  #define REG_SSC_VERSION                  (0x400040FCU) /**< \brief (SSC) Version Register */\r
+#else\r
+  #define REG_SSC_CR      (*(__O  uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */\r
+  #define REG_SSC_CMR     (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+  #define REG_SSC_RCMR    (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+  #define REG_SSC_RFMR    (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+  #define REG_SSC_TCMR    (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+  #define REG_SSC_TFMR    (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+  #define REG_SSC_RHR     (*(__I  uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+  #define REG_SSC_THR     (*(__O  uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+  #define REG_SSC_RSHR    (*(__I  uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+  #define REG_SSC_TSHR    (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+  #define REG_SSC_RC0R    (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+  #define REG_SSC_RC1R    (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+  #define REG_SSC_SR      (*(__I  uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */\r
+  #define REG_SSC_IER     (*(__O  uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+  #define REG_SSC_IDR     (*(__O  uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+  #define REG_SSC_IMR     (*(__I  uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+  #define REG_SSC_WPMR    (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+  #define REG_SSC_WPSR    (*(__I  uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+  #define REG_SSC_VERSION (*(__I  uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM_SSC_INSTANCE_ */\r