--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup dmac_module Working with DMAC\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable or disable the a DMAC controller with DMAC_Enable() and or DMAC_Disable().</li>\r
+ * <li> Enable or disable %Dma interrupt using DMAC_EnableIt()or DMAC_DisableIt().</li>\r
+ * <li> Get %Dma interrupt status by DMAC_GetStatus() and DMAC_GetInterruptMask().</li>\r
+ * <li> Enable or disable specified %Dma channel with DMAC_EnableChannel() or DMAC_DisableChannel().</li>\r
+ * <li> Get %Dma channel status by DMAC_GetChannelStatus().</li>\r
+ * <li> ControlA and ControlB register is set by DMAC_SetControlA() and DMAC_SetControlB().</li>\r
+ * <li> Configure source and/or destination start address with DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().</li>\r
+ * <li> Set %Dma descriptor address using DMAC_SetDescriptorAddr().</li>\r
+ * <li> Set source transfer buffer size with DMAC_SetBufferSize().</li>\r
+ * <li> Configure source and/or destination Picture-In-Picutre mode with DMAC_SetSourcePip() and/or DMAC_SetDestPip().</li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the DMAC section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref dmad_module\r
+ *\r
+ * Related files :\n\r
+ * \ref dmac.c\n\r
+ * \ref dmac.h.\n\r
+ *\r
+ */\r
+\r
+#ifndef DMAC_H\r
+#define DMAC_H\r
+/**@{*/\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_defines DMAC Definitions\r
+ * @{\r
+ */\r
+/** Number of DMA channels */\r
+#define XDMAC_CONTROLLER_NUM 1\r
+/** Number of DMA channels */\r
+#define XDMAC_CHANNEL_NUM 24\r
+/** Max DMA single transfer size */\r
+#define XDMAC_MAX_BT_SIZE 0xFFFF\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macro\r
+ *----------------------------------------------------------------------------*/\r
+#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \\r
+ ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \\r
+ (XDMAC_CC_DWIDTH_WORD )))\r
+#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \\r
+ ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \\r
+ ((s==2)? XDMAC_CC_SAM_UBS_AM : XDMAC_CC_SAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \\r
+ ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \\r
+ ((d==2)? XDMAC_CC_DAM_UBS_AM : XDMAC_CC_DAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : XDMAC_CC_MEMSET_HW_MODE)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Data structs\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_struct DMAC Data Structs\r
+ * @{\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+/** \addtogroup dmac_functions\r
+ * @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+extern uint32_t XDMAC_GetType( Xdmac *pXdmac);\r
+extern uint32_t XDMAC_GetConfig( Xdmac *pXdmac);\r
+extern uint32_t XDMAC_GetArbiter( Xdmac *pXdmac);\r
+extern void XDMAC_EnableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask );\r
+extern void XDMAC_DisableGIt (Xdmac *pXdmac, uint32_t dwInteruptMask );\r
+extern uint32_t XDMAC_GetGItMask( Xdmac *pXdmac );\r
+extern uint32_t XDMAC_GetGIsr( Xdmac *pXdmac );\r
+extern uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac );\r
+extern void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_EnableChannels( Xdmac *pXdmac, uint8_t bmChannels );\r
+extern void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_DisableChannels( Xdmac *pXdmac, uint8_t bmChannels );\r
+extern uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac);\r
+extern void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel );\r
+extern void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac);\r
+extern void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask );\r
+extern void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, uint32_t dwInteruptMask );\r
+extern uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel);\r
+extern uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr);\r
+extern void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr);\r
+extern void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr, uint32_t ndaif);\r
+extern void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint32_t config);\r
+extern void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen);\r
+extern void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint32_t blen);\r
+extern void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config);\r
+extern uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel);\r
+extern void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, uint32_t dds_msp);\r
+extern void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t subs);\r
+extern void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t dubs);\r
+extern uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @}*/\r
+/**@}*/\r
+#endif //#ifndef DMAC_H\r
+\r
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