+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32_hal_legacy.h\r
- * @author MCD Application Team\r
- * @version V0.3.0\r
- * @date 06-March-2015\r
- * @brief This file contains aliases definition for the STM32Cube HAL constants \r
- * macros and functions maintained for legacy purpose.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32_HAL_LEGACY\r
-#define __STM32_HAL_LEGACY\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
-#define REGULAR_GROUP ADC_REGULAR_GROUP\r
-#define INJECTED_GROUP ADC_INJECTED_GROUP\r
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
-#define AWD_EVENT ADC_AWD_EVENT\r
-#define AWD1_EVENT ADC_AWD1_EVENT\r
-#define AWD2_EVENT ADC_AWD2_EVENT\r
-#define AWD3_EVENT ADC_AWD3_EVENT\r
-#define OVR_EVENT ADC_OVR_EVENT\r
-#define JQOVF_EVENT ADC_JQOVF_EVENT\r
-#define ALL_CHANNELS ADC_ALL_CHANNELS\r
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO \r
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 \r
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO \r
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 \r
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING \r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */ \r
- \r
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG \r
-\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
-#define DAC_WAVE_NONE ((uint32_t)0x00000000)\r
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)\r
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) \r
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
-#define OBEX_PCROP OPTIONBYTE_PCROP\r
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
-#define PAGESIZE FLASH_PAGE_SIZE\r
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
-#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
-#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
-#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
-#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
-#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
-#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
-#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-\r
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
- * @{\r
- */\r
-#if defined(STM32L4) || defined(STM32F7)\r
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
-#else\r
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
-#define GET_GPIO_INDEX GPIO_GET_INDEX\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
-\r
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
-\r
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS\r
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS\r
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define NAND_AddressTypedef NAND_AddressTypeDef\r
-\r
-#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
-#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
-\r
-#define __NOR_WRITE NOR_WRITE\r
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
- \r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 \r
-\r
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
-\r
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 \r
-\r
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
- \r
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO \r
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 \r
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 \r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-/* Compact Flash-ATA registers description */\r
-#define CF_DATA ATA_DATA \r
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT \r
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER \r
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW \r
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH \r
-#define CF_CARD_HEAD ATA_CARD_HEAD \r
-#define CF_STATUS_CMD ATA_STATUS_CMD \r
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA \r
-\r
-/* Compact Flash-ATA commands */\r
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD \r
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
-\r
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define FORMAT_BIN RTC_FORMAT_BIN\r
-#define FORMAT_BCD RTC_FORMAT_BCD\r
-\r
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
-\r
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE \r
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE \r
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE \r
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT \r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
-\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
-\r
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
-/**\r
- * @}\r
- */\r
-\r
- \r
- /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
-/**\r
- * @}\r
- */\r
- \r
- /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
-\r
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
-\r
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
- \r
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
-#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
-#define TIM_DMABase_SR TIM_DMABASE_SR\r
-#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
-#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
-#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
-#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
-#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
-#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
-#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
-#define TIM_DMABase_OR TIM_DMABASE_OR\r
-\r
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
-\r
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
-\r
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
-\r
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
-\r
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
-\r
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
-\r
-#define USARTNACK_ENABLED USART_NACK_ENABLE\r
-#define USARTNACK_DISABLED USART_NACK_DISABLE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CFR_BASE WWDG_CFR_BASE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
-#define CAN_IT_RQCP0 CAN_IT_TME\r
-#define CAN_IT_RQCP1 CAN_IT_TME\r
-#define CAN_IT_RQCP2 CAN_IT_TME\r
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)\r
-#define CAN_TXSTATUS_OK ((uint8_t)0x01)\r
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define VLAN_TAG ETH_VLAN_TAG\r
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
-\r
-#define ETH_MMCCR ((uint32_t)0x00000100) \r
-#define ETH_MMCRIR ((uint32_t)0x00000104) \r
-#define ETH_MMCTIR ((uint32_t)0x00000108) \r
-#define ETH_MMCRIMR ((uint32_t)0x0000010C) \r
-#define ETH_MMCTIMR ((uint32_t)0x00000110) \r
-#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) \r
-#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) \r
-#define ETH_MMCTGFCR ((uint32_t)0x00000168) \r
-#define ETH_MMCRFCECR ((uint32_t)0x00000194) \r
-#define ETH_MMCRFAECR ((uint32_t)0x00000198) \r
-#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
- * @{\r
- */ \r
- \r
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
-\r
-/*HASH Algorithm Selection*/\r
-\r
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 \r
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
-\r
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH \r
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
-\r
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
-\r
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
- /**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
-\r
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
-\r
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
-\r
-#define DBP_BitNumber DBP_BIT_NUMBER\r
-#define PVDE_BitNumber PVDE_BIT_NUMBER\r
-#define PMODE_BitNumber PMODE_BIT_NUMBER\r
-#define EWUP_BitNumber EWUP_BIT_NUMBER\r
-#define FPDS_BitNumber FPDS_BIT_NUMBER\r
-#define ODEN_BitNumber ODEN_BIT_NUMBER\r
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
-#define BRE_BitNumber BRE_BIT_NUMBER\r
-\r
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
- \r
- /**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback \r
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
-#define HAL_TIM_DMAError TIM_DMAError\r
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
- * @{\r
- */ \r
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
-/**\r
- * @}\r
- */\r
- \r
- \r
- /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macros ------------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define AES_IT_CC CRYP_IT_CC\r
-#define AES_IT_ERR CRYP_IT_ERR\r
-#define AES_FLAG_CCF CRYP_FLAG_CCF\r
-/**\r
- * @}\r
- */ \r
- \r
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM \r
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
-\r
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __ADC_ENABLE __HAL_ADC_ENABLE\r
-#define __ADC_DISABLE __HAL_ADC_DISABLE\r
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
-#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
-\r
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
-\r
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
-\r
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
-\r
-#define __HAL_ADC_SQR1 ADC_SQR1\r
-#define __HAL_ADC_SMPR1 ADC_SMPR1\r
-#define __HAL_ADC_SMPR2 ADC_SMPR2\r
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
-#define __HAL_ADC_JSQR ADC_JSQR\r
-\r
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
-\r
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
-\r
-\r
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
- ((WAVE) == DAC_WAVE_NOISE)|| \\r
- ((WAVE) == DAC_WAVE_TRIANGLE))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define IS_WRPAREA IS_OB_WRPAREA\r
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
-#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
-#define __HAL_I2C_SPEED I2C_SPEED\r
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
-\r
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
-\r
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE \r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
-\r
-/**\r
- * @}\r
- */\r
- \r
- \r
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()\r
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()\r
-#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
-\r
-#if defined (STM32F4)\r
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() \r
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG \r
-#endif /* STM32F4 */\r
-/** \r
- * @}\r
- */ \r
- \r
- \r
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
-\r
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
-\r
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE \r
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE \r
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
-#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE\r
-#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE\r
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE\r
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE \r
-#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET\r
-#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET\r
-#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE\r
-#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE\r
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE\r
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE \r
-#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET\r
-#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET\r
-#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE\r
-#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE\r
-#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET\r
-#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET\r
-#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE\r
-#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE\r
-#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET\r
-#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET\r
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
-\r
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE \r
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE \r
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE \r
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE \r
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE \r
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE \r
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE \r
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE \r
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE \r
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE \r
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE \r
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE \r
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE \r
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE \r
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE \r
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE \r
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE \r
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE \r
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE \r
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE \r
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE \r
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE \r
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE \r
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE \r
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE \r
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE \r
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET \r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE \r
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET \r
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE \r
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE \r
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE \r
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE \r
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE \r
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE \r
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE \r
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
-\r
-/* alias define maintained for legacy */\r
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
-\r
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
-\r
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
-\r
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
-\r
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
-#define RCC_MCO_NODIV RCC_MCODIV_1\r
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
-\r
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
-\r
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
-\r
-#define CR_HSION_BB RCC_CR_HSION_BB\r
-#define CR_CSSON_BB RCC_CR_CSSON_BB\r
-#define CR_PLLON_BB RCC_CR_PLLON_BB\r
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
-#define CR_MSION_BB RCC_CR_MSION_BB\r
-#define CSR_LSION_BB RCC_CSR_LSION_BB\r
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) \r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
-\r
-#if defined (STM32F1)\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
-\r
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
-\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
-#else\r
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
-#endif /* STM32F1 */\r
-\r
-#define IS_ALARM IS_RTC_ALARM\r
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
-#define IS_TAMPER IS_RTC_TAMPER\r
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER \r
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
-\r
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
-\r
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
-\r
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
-\r
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
-\r
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE \r
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-\r
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
-#define __USART_ENABLE __HAL_USART_ENABLE\r
-#define __USART_DISABLE __HAL_USART_DISABLE\r
-\r
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
-\r
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
-\r
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
-\r
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-\r
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
-\r
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
-\r
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
-\r
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
-\r
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
-\r
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
-\r
-#define TIM_TS_ITR0 ((uint32_t)0x0000)\r
-#define TIM_TS_ITR1 ((uint32_t)0x0010)\r
-#define TIM_TS_ITR2 ((uint32_t)0x0020)\r
-#define TIM_TS_ITR3 ((uint32_t)0x0030)\r
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3))\r
-\r
-#define TIM_CHANNEL_1 ((uint32_t)0x0000)\r
-#define TIM_CHANNEL_2 ((uint32_t)0x0004)\r
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\r
- ((CHANNEL) == TIM_CHANNEL_2))\r
-\r
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)\r
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)\r
-\r
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \\r
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))\r
-\r
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)\r
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)\r
-\r
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \\r
- ((STATE) == TIM_OUTPUTSTATE_ENABLE)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
-\r
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE \r
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define __HAL_LTDC_LAYER LTDC_LAYER\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
-#define SAI_STREOMODE SAI_STEREOMODE\r
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY \r
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL \r
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL \r
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL \r
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL \r
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL \r
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* ___STM32_HAL_LEGACY */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
projects / freertos / blobdiff