--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @version V0.3.0\r
+ * @date 06-March-2015\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_H\r
+#define __STM32F7xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @brief DMA Exported Types \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream. \r
+ This parameter can be a value of @ref DMA_Channel_selection */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, \r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+\r
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r
+ This parameter can be a value of @ref DMA_FIFO_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the \r
+ memory-to-memory data transfer is configured on the selected stream */\r
+\r
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */\r
+\r
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Memory_burst \r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction. \r
+ This parameter can be a value of @ref DMA_Peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+}DMA_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */\r
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */\r
+ HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */\r
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */\r
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */\r
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */\r
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+/** \r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */ \r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */ \r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */ \r
+\r
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */\r
+\r
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @brief DMA Error Code \r
+ * @{\r
+ */ \r
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */\r
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */\r
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */\r
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */\r
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Channel_selection DMA Channel selection\r
+ * @brief DMA channel selection \r
+ * @{\r
+ */ \r
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */\r
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */\r
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */\r
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */\r
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */\r
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */\r
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */\r
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @brief DMA data transfer direction \r
+ * @{\r
+ */ \r
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @brief DMA peripheral incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */\r
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @brief DMA memory incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */\r
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @brief DMA peripheral data size \r
+ * @{\r
+ */ \r
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */\r
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\r
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @brief DMA memory data size \r
+ * @{ \r
+ */\r
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */\r
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\r
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @brief DMA mode \r
+ * @{\r
+ */ \r
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */\r
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */\r
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @brief DMA priority levels \r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */\r
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */\r
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */\r
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r
+ * @brief DMA FIFO direct mode\r
+ * @{\r
+ */\r
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */\r
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r
+ * @brief DMA FIFO level \r
+ * @{\r
+ */\r
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */\r
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */\r
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */\r
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_burst DMA Memory burst\r
+ * @brief DMA memory burst \r
+ * @{\r
+ */ \r
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000) \r
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) \r
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) \r
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r
+ * @brief DMA peripheral burst \r
+ * @{\r
+ */ \r
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000) \r
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) \r
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) \r
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @brief DMA interrupts definition \r
+ * @{\r
+ */\r
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)\r
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)\r
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)\r
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)\r
+#define DMA_IT_FE ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @brief DMA flag definitions \r
+ * @{\r
+ */ \r
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)\r
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)\r
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)\r
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)\r
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)\r
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)\r
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)\r
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)\r
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)\r
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)\r
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)\r
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)\r
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)\r
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)\r
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)\r
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)\r
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)\r
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)\r
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)\r
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @brief Reset DMA handle state\r
+ * @param __HANDLE__: specifies the DMA handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO filled level.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The FIFO filling state.\r
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r
+ * and not empty.\r
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r
+ * - DMA_FIFOStatus_Empty: when FIFO is empty\r
+ * - DMA_FIFOStatus_Full: when FIFO is full\r
+ */\r
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ DMA_FLAG_TCIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream half transfer complete flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */ \r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ DMA_FLAG_HTIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ DMA_FLAG_TEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified FIFO error flag index.\r
+ */\r
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ DMA_FLAG_FEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream direct mode error flag.\r
+ * @param __HANDLE__: DMA handle\r
+ * @retval The specified direct mode error flag index.\r
+ */\r
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ DMA_FLAG_DMEIF3_7)\r
+\r
+/**\r
+ * @brief Get the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Stream pending flags.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __FLAG__: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Stream interrupt has occurred or not.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval The state of DMA_IT.\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\r
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Writes the number of data units to be transferred on the DMA Stream.\r
+ * @param __HANDLE__: DMA handle\r
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) \r
+ * Number of data items depends only on the Peripheral data format.\r
+ * \r
+ * @note If Peripheral data format is Bytes: number of data units is equal \r
+ * to total number of bytes to be transferred.\r
+ * \r
+ * @note If Peripheral data format is Half-Word: number of data units is \r
+ * equal to total number of bytes to be transferred / 2.\r
+ * \r
+ * @note If Peripheral data format is Word: number of data units is equal \r
+ * to total number of bytes to be transferred / 4.\r
+ * \r
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.\r
+ */\r
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r
+ * @param __HANDLE__: DMA handle\r
+ * \r
+ * @retval The number of remaining data units in the current DMA Stream transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r
+\r
+\r
+/* Include DMA HAL Extension module */\r
+#include "stm32f7xx_hal_dma_ex.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @brief DMA Exported functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r
+ * @brief I/O operation functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ * @{\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+/* Private Constants -------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Constants DMA Private Constants\r
+ * @brief DMA private defines and constants \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @brief DMA private macros \r
+ * @{\r
+ */\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7))\r
+\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR) || \\r
+ ((MODE) == DMA_PFCTRL)) \r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\r
+ ((STATE) == DMA_FIFOMODE_ENABLE))\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\r
+ ((BURST) == DMA_MBURST_INC4) || \\r
+ ((BURST) == DMA_MBURST_INC8) || \\r
+ ((BURST) == DMA_MBURST_INC16))\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\r
+ ((BURST) == DMA_PBURST_INC4) || \\r
+ ((BURST) == DMA_PBURST_INC8) || \\r
+ ((BURST) == DMA_PBURST_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @brief DMA private functions \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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