+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f7xx_hal_qspi.c\r
- * @author MCD Application Team\r
- * @version V0.3.0\r
- * @date 06-March-2015\r
- * @brief QSPI HAL module driver.\r
- *\r
- * This file provides firmware functions to manage the following \r
- * functionalities of the QuadSPI interface (QSPI).\r
- * + Initialization and de-initialization functions\r
- * + Indirect functional mode management\r
- * + Memory-mapped functional mode management\r
- * + Auto-polling functional mode management\r
- * + Interrupts and flags management\r
- * + DMA channel configuration for indirect functional mode\r
- * + Errors management and abort functionality\r
- *\r
- *\r
- @verbatim\r
- ===============================================================================\r
- ##### How to use this driver #####\r
- ===============================================================================\r
- [..]\r
- *** Initialization ***\r
- ======================\r
- [..]\r
- (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r
- (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r
- (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r
- (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r
- (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r
- (+) If interrupt mode is used, enable and configure QuadSPI global\r
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
- (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel \r
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), \r
- link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure \r
- DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r
- (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r
- clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r
-\r
- *** Indirect functional mode ***\r
- ================================\r
- [..]\r
- (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() \r
- functions :\r
- (+) Instruction phase : the mode used and if present the instruction opcode.\r
- (+) Address phase : the mode used and if present the size and the address value.\r
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
- bytes values.\r
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
- (+) Data phase : the mode used and if present the number of bytes.\r
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
- if activated.\r
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
- (#) If no data is required for the command, it is sent directly to the memory :\r
- (+) In polling mode, the output of the function is done when the transfer is complete.\r
- (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r
- (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or \r
- HAL_QSPI_Transmit_IT() after the command configuration :\r
- (+) In polling mode, the output of the function is done when the transfer is complete.\r
- (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
- is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
- (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and \r
- HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r
- (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or \r
- HAL_QSPI_Receive_IT() after the command configuration :\r
- (+) In polling mode, the output of the function is done when the transfer is complete.\r
- (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r
- is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
- (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and \r
- HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r
-\r
- *** Auto-polling functional mode ***\r
- ====================================\r
- [..]\r
- (#) Configure the command sequence and the auto-polling functional mode using the \r
- HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r
- (+) Instruction phase : the mode used and if present the instruction opcode.\r
- (+) Address phase : the mode used and if present the size and the address value.\r
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
- bytes values.\r
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
- (+) Data phase : the mode used.\r
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
- if activated.\r
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
- (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r
- the polling interval and the automatic stop activation.\r
- (#) After the configuration :\r
- (+) In polling mode, the output of the function is done when the status match is reached. The\r
- automatic stop is activated to avoid an infinite loop.\r
- (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r
-\r
- *** Memory-mapped functional mode ***\r
- =====================================\r
- [..]\r
- (#) Configure the command sequence and the memory-mapped functional mode using the \r
- HAL_QSPI_MemoryMapped() functions :\r
- (+) Instruction phase : the mode used and if present the instruction opcode.\r
- (+) Address phase : the mode used and the size.\r
- (+) Alternate-bytes phase : the mode used and if present the size and the alternate \r
- bytes values.\r
- (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r
- (+) Data phase : the mode used.\r
- (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r
- if activated.\r
- (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r
- (+) The timeout activation and the timeout period.\r
- (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on \r
- the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r
-\r
- *** Errors management and abort functionality ***\r
- ==================================================\r
- [..]\r
- (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r
- (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.\r
- (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r
-\r
- *** Workarounds linked to Silicon Limitation ***\r
- ====================================================\r
- [..]\r
- (#) Workarounds Implemented inside HAL Driver\r
- (+) Extra data written in the FIFO at the end of a read transfer\r
-\r
- @endverbatim\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ****************************************************************************** \r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f7xx_hal.h"\r
-\r
-/** @addtogroup STM32F7xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup QSPI QSPI\r
- * @brief HAL QSPI module driver\r
- * @{\r
- */\r
-#ifdef HAL_QSPI_MODULE_ENABLED\r
- \r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private define ------------------------------------------------------------*/\r
-/** @addtogroup QSPI_Private_Constants \r
- * @{\r
- */\r
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/\r
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r
-#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r
-#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/\r
-/**\r
- * @}\r
- */\r
- \r
-/* Private macro -------------------------------------------------------------*/\r
-/** @addtogroup QSPI_Private_Macros QSPI Private Macros\r
- * @{\r
- */\r
-#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\r
- ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \\r
- ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \\r
- ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
-/**\r
- * @}\r
- */\r
- \r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @addtogroup QSPI_Private_Functions QSPI Private Functions\r
- * @{\r
- */\r
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma); \r
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);\r
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r
-/**\r
- * @}\r
- */\r
- \r
-/* Exported functions ---------------------------------------------------------*/\r
-\r
-/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions \r
- * @brief Initialization and Configuration functions \r
- *\r
-@verbatim \r
-===============================================================================\r
- ##### Initialization and Configuration functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to :\r
- (+) Initialize the QuadSPI.\r
- (+) De-initialize the QuadSPI.\r
- \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initializes the QSPI mode according to the specified parameters\r
- * in the QSPI_InitTypeDef and creates the associated handle.\r
- * @param hqspi: qspi handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the QSPI handle allocation */\r
- if(hqspi == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r
- assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r
- assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r
- assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r
- assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r
- assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r
- assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r
- assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r
- assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_RESET)\r
- { \r
- /* Init the low level hardware : GPIO, CLOCK */\r
- HAL_QSPI_MspInit(hqspi);\r
- \r
- /* Configure the default timeout for the QSPI memory access */\r
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);\r
- }\r
- \r
- /* Configure QSPI FIFO Threshold */\r
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));\r
-\r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
- \r
- if(status == HAL_OK)\r
- {\r
- \r
- /* Configure QSPI Clock Prescaler and Sample Shift */\r
- MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));\r
- \r
- /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r
- MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), \r
- ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r
- \r
- /* Enable the QSPI peripheral */\r
- __HAL_QSPI_ENABLE(hqspi);\r
- \r
- /* Set QSPI error code to none */\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; \r
-\r
- /* Initialize the QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- }\r
- \r
- /* Release Lock */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- /* Return function status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief DeInitializes the QSPI peripheral \r
- * @param hqspi: qspi handle\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* Check the QSPI handle allocation */\r
- if(hqspi == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
-\r
- /* Disable the QSPI Peripheral Clock */\r
- __HAL_QSPI_DISABLE(hqspi);\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
- HAL_QSPI_MspDeInit(hqspi);\r
-\r
- /* Set QSPI error code to none */\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
- /* Initialize the QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief QSPI MSP Init\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
- __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_QSPI_MspInit can be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @brief QSPI MSP DeInit\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
- __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_QSPI_MspDeInit can be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions \r
- * @brief QSPI Transmit/Receive functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### I/O operation functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to :\r
- (+) Handle the interrupts.\r
- (+) Handle the command sequence.\r
- (+) Transmit data in blocking, interrupt or DMA mode.\r
- (+) Receive data in blocking, interrupt or DMA mode.\r
- (+) Manage the auto-polling functional mode.\r
- (+) Manage the memory-mapped functional mode.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief This function handles QSPI interrupt request.\r
- * @param hqspi: QSPI handle\r
- * @retval None.\r
- */\r
-void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r
-{\r
- __IO uint32_t *data_reg;\r
- uint32_t flag = 0, itsource = 0;\r
-\r
- /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/\r
- flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);\r
- itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);\r
- \r
- if((flag != RESET) && (itsource != RESET))\r
- {\r
- data_reg = &hqspi->Instance->DR;\r
-\r
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
- {\r
- /* Transmission process */\r
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
- {\r
- if (hqspi->TxXferCount > 0)\r
- {\r
- /* Fill the FIFO until it is full */\r
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
- hqspi->TxXferCount--;\r
- }\r
- else\r
- {\r
- /* No more data available for the transfer */\r
- break;\r
- }\r
- }\r
- }\r
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
- {\r
- /* Receiving Process */\r
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r
- {\r
- if (hqspi->RxXferCount > 0)\r
- {\r
- /* Read the FIFO until it is empty */\r
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
- hqspi->RxXferCount--;\r
- }\r
- else\r
- {\r
- /* All data have been received for the transfer */\r
- break;\r
- }\r
- }\r
- }\r
- \r
- /* FIFO Threshold callback */\r
- HAL_QSPI_FifoThresholdCallback(hqspi);\r
- }\r
-\r
- /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r
- flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);\r
- itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);\r
- \r
- if((flag != RESET) && (itsource != RESET))\r
- {\r
- /* Clear interrupt */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
- /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
- \r
- /* Transfer complete callback */\r
- if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r
- {\r
- /* Clear Busy bit */\r
- HAL_QSPI_Abort(hqspi);\r
- \r
- /* TX Complete callback */\r
- HAL_QSPI_TxCpltCallback(hqspi);\r
- }\r
- else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r
- {\r
- data_reg = &hqspi->Instance->DR;\r
- while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)\r
- {\r
- if (hqspi->RxXferCount > 0)\r
- {\r
- /* Read the last data received in the FIFO until it is empty */\r
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
- hqspi->RxXferCount--;\r
- }\r
- else\r
- {\r
- /* All data have been received for the transfer */\r
- break;\r
- }\r
- }\r
-\r
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
- HAL_QSPI_Abort(hqspi);\r
- \r
- /* RX Complete callback */\r
- HAL_QSPI_RxCpltCallback(hqspi);\r
- }\r
- else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r
- {\r
- /* Command Complete callback */\r
- HAL_QSPI_CmdCpltCallback(hqspi);\r
- }\r
-\r
- /* Change state of QSPI */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- }\r
-\r
- /* QSPI Status Match interrupt occurred ------------------------------------*/\r
- flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);\r
- itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);\r
- \r
- if((flag != RESET) && (itsource != RESET))\r
- {\r
- /* Clear interrupt */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
- \r
- /* Check if the automatic poll mode stop is activated */\r
- if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)\r
- {\r
- /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */\r
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);\r
-\r
- /* Change state of QSPI */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- }\r
-\r
- /* Status match callback */\r
- HAL_QSPI_StatusMatchCallback(hqspi);\r
- }\r
-\r
- /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r
- flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);\r
- itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);\r
- \r
- if((flag != RESET) && (itsource != RESET))\r
- {\r
- /* Clear interrupt */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);\r
- \r
- /* Disable all the QSPI Interrupts */\r
- __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r
-\r
- /* Set error code */\r
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r
- \r
- /* Change state of QSPI */\r
- hqspi->State = HAL_QSPI_STATE_ERROR;\r
-\r
- /* Error callback */\r
- HAL_QSPI_ErrorCallback(hqspi);\r
- }\r
-\r
- /* QSPI Time out interrupt occurred -----------------------------------------*/\r
- flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);\r
- itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);\r
- \r
- if((flag != RESET) && (itsource != RESET))\r
- {\r
- /* Clear interrupt */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r
- \r
- /* Time out callback */\r
- HAL_QSPI_TimeOutCallback(hqspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the command configuration. \r
- * @param hqspi: QSPI handle\r
- * @param cmd : structure that contains the command configuration information\r
- * @param Timeout : Time out duration\r
- * @note This function is used only in Indirect Read or Write Modes\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
- }\r
-\r
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
- }\r
-\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
- }\r
-\r
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY; \r
- \r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Call the configuration function */\r
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
- \r
- if (cmd->DataMode == QSPI_DATA_NONE)\r
- {\r
- /* When there is no data phase, the transfer start as soon as the configuration is done \r
- so wait until TC flag is set to go back in idle state */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- }\r
- else\r
- {\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
- \r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY; \r
- }\r
- \r
- }\r
- else\r
- {\r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY; \r
- }\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
- \r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- /* Return function status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Sets the command configuration in interrupt mode. \r
- * @param hqspi: QSPI handle\r
- * @param cmd : structure that contains the command configuration information\r
- * @note This function is used only in Indirect Read or Write Modes\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
- }\r
-\r
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
- }\r
-\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
- }\r
-\r
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
-\r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY; \r
- \r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
- \r
- if (status == HAL_OK)\r
- {\r
- if (cmd->DataMode == QSPI_DATA_NONE)\r
- {\r
- /* When there is no data phase, the transfer start as soon as the configuration is done \r
- so activate TC and TE interrupts */\r
- /* Enable the QSPI Transfer Error Interrupt */\r
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r
- }\r
- \r
- /* Call the configuration function */\r
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
- \r
- if (cmd->DataMode != QSPI_DATA_NONE)\r
- {\r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY; \r
- }\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
- \r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- /* Return function status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Transmit an amount of data in blocking mode. \r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer\r
- * @param Timeout : Time out duration\r
- * @note This function is used only in Indirect Write Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL )\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
- \r
- /* Configure counters and size of the handle */\r
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pTxBuffPtr = pData;\r
- \r
- /* Configure QSPI: CCR register with functional as indirect write */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
-\r
- while(hqspi->TxXferCount > 0)\r
- {\r
- /* Wait until FT flag is set to send data */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- break;\r
- }\r
-\r
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r
- hqspi->TxXferCount--;\r
- }\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Wait until TC flag is set to go back in idle state */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- }\r
- else\r
- {\r
- /* Clear Transfer Complete bit */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
- \r
- /* Clear Busy bit */\r
- status = HAL_QSPI_Abort(hqspi);\r
- }\r
- }\r
- \r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY; \r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY;\r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
-\r
-\r
-/**\r
- * @brief Receive an amount of data in blocking mode \r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer\r
- * @param Timeout : Time out duration\r
- * @note This function is used only in Indirect Read Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
- __IO uint32_t *data_reg = &hqspi->Instance->DR;\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL )\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
- \r
- /* Configure counters and size of the handle */\r
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pRxBuffPtr = pData;\r
-\r
- /* Configure QSPI: CCR register with functional as indirect read */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
- /* Start the transfer by re-writing the address in AR register */\r
- WRITE_REG(hqspi->Instance->AR, addr_reg);\r
- \r
- while(hqspi->RxXferCount > 0)\r
- {\r
- /* Wait until FT or TC flag is set to read received data */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- break;\r
- }\r
-\r
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r
- hqspi->RxXferCount--;\r
- }\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Wait until TC flag is set to go back in idle state */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- }\r
- else\r
- {\r
- /* Clear Transfer Complete bit */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
- \r
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
- status = HAL_QSPI_Abort(hqspi);\r
- }\r
- }\r
-\r
- /* Update QSPI state */\r
- hqspi->State = HAL_QSPI_STATE_READY; \r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY;\r
- }\r
- \r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Send an amount of data in interrupt mode \r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer\r
- * @note This function is used only in Indirect Write Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{ \r
- HAL_StatusTypeDef status = HAL_OK;\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
-\r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL )\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
-\r
- /* Configure counters and size of the handle */\r
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pTxBuffPtr = pData;\r
- \r
- /* Configure QSPI: CCR register with functional as indirect write */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
- \r
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
- \r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY;\r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Receive an amount of data in no-blocking mode with Interrupt\r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer\r
- * @note This function is used only in Indirect Read Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
-\r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL )\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
- \r
- /* Configure counters and size of the handle */\r
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pRxBuffPtr = pData;\r
-\r
- /* Configure QSPI: CCR register with functional as indirect read */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
- /* Start the transfer by re-writing the address in AR register */\r
- WRITE_REG(hqspi->Instance->AR, addr_reg);\r
-\r
- /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Sends an amount of data in non blocking mode with DMA. \r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer\r
- * @note This function is used only in Indirect Write Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint32_t *tmp;\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL ) \r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
-\r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r
-\r
- /* Configure counters and size of the handle */\r
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pTxBuffPtr = pData;\r
- \r
- /* Configure QSPI: CCR register with functional mode as indirect write */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r
- \r
- /* Set the QSPI DMA transfer complete callback */\r
- hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r
- \r
- /* Set the QSPI DMA Half transfer complete callback */\r
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r
- \r
- /* Set the DMA error callback */\r
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
- \r
- /* Configure the direction of the DMA */\r
- hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
-\r
- /* Enable the QSPI transmit DMA Channel */\r
- tmp = (uint32_t*)&pData;\r
- HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);\r
- \r
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
- }\r
- else\r
- {\r
- status = HAL_OK;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
- \r
-/**\r
- * @brief Receives an amount of data in non blocking mode with DMA. \r
- * @param hqspi: QSPI handle\r
- * @param pData: pointer to data buffer.\r
- * @note This function is used only in Indirect Read Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
- uint32_t *tmp;\r
- uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- if(pData != NULL ) \r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r
- \r
- /* Configure counters and size of the handle */\r
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r
- hqspi->pRxBuffPtr = pData;\r
-\r
- /* Set the QSPI DMA transfer complete callback */\r
- hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r
- \r
- /* Set the QSPI DMA Half transfer complete callback */\r
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r
- \r
- /* Set the DMA error callback */\r
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r
- \r
- /* Configure the direction of the DMA */\r
- hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r
-\r
- /* Enable the DMA Channel */\r
- tmp = (uint32_t*)&pData;\r
- HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);\r
- \r
- /* Configure QSPI: CCR register with functional as indirect read */\r
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r
-\r
- /* Start the transfer by re-writing the address in AR register */\r
- WRITE_REG(hqspi->Instance->AR, addr_reg);\r
-\r
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
- }\r
- else\r
- {\r
- status = HAL_ERROR;\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
-\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Configure the QSPI Automatic Polling Mode in blocking mode. \r
- * @param hqspi: QSPI handle\r
- * @param cmd: structure that contains the command configuration information.\r
- * @param cfg: structure that contains the polling configuration information.\r
- * @param Timeout : Time out duration\r
- * @note This function is used only in Automatic Polling Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
- }\r
-\r
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
- }\r
-\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
- }\r
-\r
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- \r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
-\r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Configure QSPI: PSMAR register with the status match value */\r
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
- \r
- /* Configure QSPI: PSMKR register with the status mask value */\r
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
- \r
- /* Configure QSPI: PIR register with the interval value */\r
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
- \r
- /* Configure QSPI: CR register with Match mode and Automatic stop enabled \r
- (otherwise there will be an infinite loop in blocking mode) */\r
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
- (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r
-\r
- /* Call the configuration function */\r
- cmd->NbData = cfg->StatusBytesSize;\r
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
-\r
- /* Wait until SM flag is set to go back in idle state */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- }\r
- else\r
- {\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r
-\r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
- \r
- /* Return function status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. \r
- * @param hqspi: QSPI handle\r
- * @param cmd: structure that contains the command configuration information.\r
- * @param cfg: structure that contains the polling configuration information.\r
- * @note This function is used only in Automatic Polling Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
- }\r
-\r
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
- }\r
-\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
- }\r
-\r
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
- assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r
- assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r
- assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r
- assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
-if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r
- \r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Configure QSPI: PSMAR register with the status match value */\r
- WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r
- \r
- /* Configure QSPI: PSMKR register with the status mask value */\r
- WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r
- \r
- /* Configure QSPI: PIR register with the interval value */\r
- WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r
- \r
- /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r
- (cfg->MatchMode | cfg->AutomaticStop));\r
-\r
- /* Call the configuration function */\r
- cmd->NbData = cfg->StatusBytesSize;\r
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r
-\r
- /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */\r
- __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));\r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
- \r
- /* Return function status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Configure the Memory Mapped mode. \r
- * @param hqspi: QSPI handle\r
- * @param cmd: structure that contains the command configuration information.\r
- * @param cfg: structure that contains the memory mapped configuration information.\r
- * @note This function is used only in Memory mapped Mode\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r
- }\r
-\r
- assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r
- }\r
-\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r
- }\r
-\r
- assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r
- assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r
-\r
- assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r
- assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r
- assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r
-\r
- assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r
- \r
- /* Process locked */\r
- __HAL_LOCK(hqspi);\r
- \r
- if(hqspi->State == HAL_QSPI_STATE_READY)\r
- {\r
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r
- \r
- /* Wait till BUSY flag reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
- \r
- if (status == HAL_OK)\r
- {\r
- /* Configure QSPI: CR register with time out counter enable */\r
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r
-\r
- if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r
- {\r
- assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r
-\r
- /* Configure QSPI: LPTR register with the low-power time out value */\r
- WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r
-\r
- /* Enable the QSPI TimeOut Interrupt */\r
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r
- }\r
-\r
- /* Call the configuration function */\r
- QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r
- \r
- }\r
- }\r
- else\r
- {\r
- status = HAL_BUSY; \r
- \r
- }\r
-\r
- /* Process unlocked */\r
- __HAL_UNLOCK(hqspi);\r
- \r
- /* Return function status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Transfer Error callbacks\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_ErrorCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Command completed callbacks.\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Rx Transfer completed callbacks.\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_RxCpltCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Tx Transfer completed callbacks.\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_TxCpltCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @brief Rx Half Transfer completed callbacks.\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Tx Half Transfer completed callbacks.\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
- __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE: This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r
- */ \r
-}\r
-\r
-/**\r
- * @brief FIFO Threshold callbacks\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Status Match callbacks\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Timeout callbacks\r
- * @param hqspi: QSPI handle\r
- * @retval None\r
- */\r
-__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r
-{\r
- /* NOTE : This function Should not be modified, when the callback is needed,\r
- the HAL_QSPI_TimeOutCallback could be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions \r
- * @brief QSPI control and State functions \r
- *\r
-@verbatim \r
- ===============================================================================\r
- ##### Peripheral Control and State functions #####\r
- =============================================================================== \r
- [..]\r
- This subsection provides a set of functions allowing to :\r
- (+) Check in run-time the state of the driver. \r
- (+) Check the error code set during last operation.\r
- (+) Abort any operation.\r
-..... \r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Return the QSPI state.\r
- * @param hqspi: QSPI handle\r
- * @retval HAL state\r
- */\r
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r
-{\r
- return hqspi->State;\r
-}\r
-\r
-/**\r
-* @brief Return the QSPI error code\r
-* @param hqspi: QSPI handle\r
-* @retval QSPI Error Code\r
-*/\r
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r
-{\r
- return hqspi->ErrorCode;\r
-}\r
-\r
-/**\r
-* @brief Abort the current transmission\r
-* @param hqspi: QSPI handle\r
-* @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r
-{\r
- HAL_StatusTypeDef status = HAL_ERROR;\r
-\r
- /* Configure QSPI: CR register with Abort request */\r
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r
-\r
- /* Wait until TC flag is set to go back in idle state */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
- { \r
- status = HAL_TIMEOUT;\r
- }\r
- else\r
- {\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
- \r
- /* Wait until BUSY flag is reset */\r
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);\r
-\r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- }\r
-\r
- return status;\r
-}\r
-\r
-/** @brief Set QSPI timeout\r
- * @param hqspi: QSPI handle.\r
- * @param Timeout: Timeout for the QSPI memory access.\r
- * @retval None\r
- */\r
-void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r
-{\r
- hqspi->Timeout = Timeout;\r
-}\r
-\r
-/**\r
-* @}\r
-*/\r
-\r
-/* Private functions ---------------------------------------------------------*/\r
- \r
-/**\r
- * @brief DMA QSPI receive process complete callback. \r
- * @param hdma: DMA handle\r
- * @retval None\r
- */\r
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) \r
-{\r
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
- hqspi->RxXferCount = 0;\r
- \r
- /* Wait for QSPI TC Flag */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
- {\r
- /* Time out Occurred */ \r
- HAL_QSPI_ErrorCallback(hqspi);\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
-\r
- /* Disable the DMA channel */\r
- HAL_DMA_Abort(hdma);\r
-\r
- /* Clear Transfer Complete bit */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
-\r
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r
- HAL_QSPI_Abort(hqspi);\r
- \r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- \r
- HAL_QSPI_RxCpltCallback(hqspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief DMA QSPI transmit process complete callback. \r
- * @param hdma: DMA handle\r
- * @retval None\r
- */\r
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) \r
-{\r
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
- hqspi->TxXferCount = 0;\r
- \r
- /* Wait for QSPI TC Flag */\r
- if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)\r
- {\r
- /* Time out Occurred */ \r
- HAL_QSPI_ErrorCallback(hqspi);\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r
- \r
- /* Disable the DMA channel */\r
- HAL_DMA_Abort(hdma);\r
-\r
- /* Clear Transfer Complete bit */\r
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r
- \r
- /* Clear Busy bit */\r
- HAL_QSPI_Abort(hqspi);\r
-\r
- /* Update state */\r
- hqspi->State = HAL_QSPI_STATE_READY;\r
- \r
- HAL_QSPI_TxCpltCallback(hqspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief DMA QSPI receive process half complete callback \r
- * @param hdma : DMA handle\r
- * @retval None\r
- */\r
-static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
-\r
- HAL_QSPI_RxHalfCpltCallback(hqspi); \r
-}\r
-\r
-/**\r
- * @brief DMA QSPI transmit process half complete callback \r
- * @param hdma : DMA handle\r
- * @retval None\r
- */\r
-static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r
-\r
- HAL_QSPI_TxHalfCpltCallback(hqspi);\r
-}\r
-\r
-/**\r
- * @brief DMA QSPI communication error callback.\r
- * @param hdma: DMA handle\r
- * @retval None\r
- */\r
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma) \r
-{\r
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r
-\r
- hqspi->RxXferCount = 0;\r
- hqspi->TxXferCount = 0;\r
- hqspi->State = HAL_QSPI_STATE_ERROR;\r
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r
-\r
- HAL_QSPI_ErrorCallback(hqspi);\r
-}\r
-\r
-/**\r
- * @brief This function wait a flag state until time out.\r
- * @param hqspi: QSPI handle\r
- * @param Flag: Flag checked\r
- * @param State: Value of the flag expected\r
- * @param Timeout: Duration of the time out\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,\r
- FlagStatus State, uint32_t Timeout)\r
-{\r
- uint32_t tickstart = HAL_GetTick();\r
- \r
- /* Wait until flag is in expected state */ \r
- while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r
- {\r
- /* Check for the Timeout */\r
- if (Timeout != HAL_MAX_DELAY)\r
- {\r
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))\r
- {\r
- hqspi->State = HAL_QSPI_STATE_ERROR;\r
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r
- \r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief This function configures the communication registers\r
- * @param hqspi: QSPI handle\r
- * @param cmd: structure that contains the command configuration information\r
- * @param FunctionalMode: functional mode to configured\r
- * This parameter can be a value of @ref QSPI_FunctionalMode\r
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r
- * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r
- * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r
- * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode \r
- * @retval None\r
- */\r
-static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r
-{\r
- assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r
-\r
- if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r
- {\r
- /* Configure QSPI: DLR register with the number of data to read or write */\r
- WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));\r
- }\r
- \r
- if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r
- {\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- /* Configure QSPI: ABR register with alternate bytes value */\r
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
-\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- /*---- Command with instruction, address and alternate bytes ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r
-\r
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
- {\r
- /* Configure QSPI: AR register with address value */\r
- WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
- }\r
- }\r
- else\r
- {\r
- /*---- Command with instruction and alternate bytes ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
- cmd->Instruction | FunctionalMode));\r
- }\r
- }\r
- else\r
- {\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- /*---- Command with instruction and address ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
- cmd->Instruction | FunctionalMode));\r
-\r
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
- {\r
- /* Configure QSPI: AR register with address value */\r
- WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
- }\r
- }\r
- else\r
- {\r
- /*---- Command with only instruction ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
- cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | \r
- FunctionalMode));\r
- }\r
- }\r
- }\r
- else\r
- {\r
- if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r
- {\r
- /* Configure QSPI: ABR register with alternate bytes value */\r
- WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r
-\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- /*---- Command with address and alternate bytes ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r
- cmd->InstructionMode | FunctionalMode));\r
-\r
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
- {\r
- /* Configure QSPI: AR register with address value */\r
- WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
- }\r
- }\r
- else\r
- {\r
- /*---- Command with only alternate bytes ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r
- FunctionalMode));\r
- }\r
- }\r
- else\r
- {\r
- if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r
- {\r
- /*---- Command with only address ----*/\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r
- FunctionalMode));\r
-\r
- if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r
- {\r
- /* Configure QSPI: AR register with address value */\r
- WRITE_REG(hqspi->Instance->AR, cmd->Address);\r
- }\r
- }\r
- else\r
- {\r
- /*---- Command with only data phase ----*/\r
- if (cmd->DataMode != QSPI_DATA_NONE)\r
- {\r
- /* Configure QSPI: CCR register with all communications parameters */\r
- WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r
- cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r
- }\r
- }\r
- }\r
- }\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_QSPI_MODULE_ENABLED */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff