+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f7xx.c\r
- * @author MCD Application Team\r
- * @version V0.3.0\r
- * @date 06-March-2015\r
- * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
- *\r
- * This file provides two functions and one global variable to be called from \r
- * user application:\r
- * - SystemInit(): This function is called at startup just after reset and \r
- * before branch to main program. This call is made inside\r
- * the "startup_stm32f7xx.s" file.\r
- *\r
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
- * by the user application to setup the SysTick \r
- * timer or configure other parameters.\r
- * \r
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
- * be called whenever the core clock is changed\r
- * during program execution.\r
- *\r
- *\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>\r
- *\r
- * Redistribution and use in source and binary forms, with or without modification,\r
- * are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
- * may be used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f7xx_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32F7xx_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32f7xx.h"\r
-\r
-#if !defined (HSE_VALUE) \r
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined (HSI_VALUE)\r
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* HSI_VALUE */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_Defines\r
- * @{\r
- */\r
-\r
-/************************* Miscellaneous Configuration ************************/\r
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted\r
- on EVAL board as data memory */\r
-/* #define DATA_IN_ExtSRAM */ \r
-/* #define DATA_IN_ExtSDRAM */\r
-\r
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)\r
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " \r
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */\r
-\r
-/*!< Uncomment the following line if you need to relocate your vector Table in\r
- Internal SRAM. */\r
-/* #define VECT_TAB_SRAM */\r
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
- This value must be a multiple of 0x200. */\r
-/******************************************************************************/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_Variables\r
- * @{\r
- */\r
-\r
- /* This variable is updated in three ways:\r
- 1) by calling CMSIS function SystemCoreClockUpdate()\r
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
- Note: If you use this function to configure the system clock; then there\r
- is no need to call the 2 first functions listed above, since SystemCoreClock\r
- variable is updated automatically.\r
- */\r
- uint32_t SystemCoreClock = 16000000;\r
- __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
- static void SystemInit_ExtMemCtl(void); \r
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F7xx_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system\r
- * Initialize the Embedded Flash Interface, the PLL and update the \r
- * SystemFrequency variable.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{\r
- /* FPU settings ------------------------------------------------------------*/\r
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
- #endif\r
- /* Reset the RCC clock configuration to the default reset state ------------*/\r
- /* Set HSION bit */\r
- RCC->CR |= (uint32_t)0x00000001;\r
-\r
- /* Reset CFGR register */\r
- RCC->CFGR = 0x00000000;\r
-\r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
- /* Reset PLLCFGR register */\r
- RCC->PLLCFGR = 0x24003010;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Disable all interrupts */\r
- RCC->CIR = 0x00000000;\r
-\r
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
- SystemInit_ExtMemCtl(); \r
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
-\r
- /* Configure the Vector Table location add offset address ------------------*/\r
-#ifdef VECT_TAB_SRAM\r
- SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
-#else\r
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
-#endif\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock variable according to Clock Register Values.\r
- * The SystemCoreClock variable contains the core clock (HCLK), it can\r
- * be used by the user application to setup the SysTick timer or configure\r
- * other parameters.\r
- * \r
- * @note Each time the core clock (HCLK) changes, this function must be called\r
- * to update SystemCoreClock variable value. Otherwise, any configuration\r
- * based on this variable will be incorrect. \r
- * \r
- * @note - The system frequency computed by this function is not the real \r
- * frequency in the chip. It is calculated based on the predefined \r
- * constant and the selected clock source:\r
- * \r
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
- * \r
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
- * \r
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
- * \r
- * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value\r
- * 16 MHz) but the real value may vary depending on the variations\r
- * in voltage and temperature. \r
- * \r
- * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value\r
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
- * frequency of the crystal used. Otherwise, this function may\r
- * have wrong result.\r
- * \r
- * - The result of this function could be not correct when using fractional\r
- * value for HSE crystal.\r
- * \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
- \r
- /* Get SYSCLK source -------------------------------------------------------*/\r
- tmp = RCC->CFGR & RCC_CFGR_SWS;\r
-\r
- switch (tmp)\r
- {\r
- case 0x00: /* HSI used as system clock source */\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- case 0x04: /* HSE used as system clock source */\r
- SystemCoreClock = HSE_VALUE;\r
- break;\r
- case 0x08: /* PLL used as system clock source */\r
-\r
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
- SYSCLK = PLL_VCO / PLL_P\r
- */ \r
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
- \r
- if (pllsource != 0)\r
- {\r
- /* HSE used as PLL clock source */\r
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
- }\r
- else\r
- {\r
- /* HSI used as PLL clock source */\r
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
- }\r
-\r
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
- SystemCoreClock = pllvco/pllp;\r
- break;\r
- default:\r
- SystemCoreClock = HSI_VALUE;\r
- break;\r
- }\r
- /* Compute HCLK frequency --------------------------------------------------*/\r
- /* Get HCLK prescaler */\r
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
- /* HCLK frequency */\r
- SystemCoreClock >>= tmp;\r
-}\r
-\r
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r
-/**\r
- * @brief Setup the external memory controller.\r
- * Called in startup_stm32f7xx.s before jump to main.\r
- * This function configures the external memories (SRAM/SDRAM)\r
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit_ExtMemCtl(void)\r
-{\r
-#if defined (DATA_IN_ExtSDRAM)\r
- register uint32_t tmpreg = 0, timeout = 0xFFFF;\r
- register uint32_t index;\r
-\r
- /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \r
- clock */\r
- RCC->AHB1ENR |= 0x000001F8;\r
- \r
- /* Connect PDx pins to FMC Alternate function */\r
- GPIOD->AFR[0] = 0x000000CC;\r
- GPIOD->AFR[1] = 0xCC000CCC;\r
- /* Configure PDx pins in Alternate function mode */ \r
- GPIOD->MODER = 0xA02A000A;\r
- /* Configure PDx pins speed to 50 MHz */ \r
- GPIOD->OSPEEDR = 0xA02A000A;\r
- /* Configure PDx pins Output type to push-pull */ \r
- GPIOD->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PDx pins */ \r
- GPIOD->PUPDR = 0x50150005;\r
-\r
- /* Connect PEx pins to FMC Alternate function */\r
- GPIOE->AFR[0] = 0xC00000CC;\r
- GPIOE->AFR[1] = 0xCCCCCCCC;\r
- /* Configure PEx pins in Alternate function mode */ \r
- GPIOE->MODER = 0xAAAA800A;\r
- /* Configure PEx pins speed to 50 MHz */ \r
- GPIOE->OSPEEDR = 0xAAAA800A;\r
- /* Configure PEx pins Output type to push-pull */ \r
- GPIOE->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PEx pins */ \r
- GPIOE->PUPDR = 0x55554005;\r
-\r
- /* Connect PFx pins to FMC Alternate function */\r
- GPIOF->AFR[0] = 0x00CCCCCC;\r
- GPIOF->AFR[1] = 0xCCCCC000;\r
- /* Configure PFx pins in Alternate function mode */ \r
- GPIOF->MODER = 0xAA800AAA;\r
- /* Configure PFx pins speed to 50 MHz */ \r
- GPIOF->OSPEEDR = 0xAA800AAA;\r
- /* Configure PFx pins Output type to push-pull */ \r
- GPIOF->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PFx pins */ \r
- GPIOF->PUPDR = 0x55400555;\r
-\r
- /* Connect PGx pins to FMC Alternate function */\r
- GPIOG->AFR[0] = 0x00CC00CC;\r
- GPIOG->AFR[1] = 0xC000000C;\r
- /* Configure PGx pins in Alternate function mode */ \r
- GPIOG->MODER = 0x80020A0A;\r
- /* Configure PGx pins speed to 50 MHz */ \r
- GPIOG->OSPEEDR = 0x80020A0A;\r
- /* Configure PGx pins Output type to push-pull */ \r
- GPIOG->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PGx pins */ \r
- GPIOG->PUPDR = 0x40010505;\r
- \r
- /* Connect PHx pins to FMC Alternate function */\r
- GPIOH->AFR[0] = 0x00C0CC00;\r
- GPIOH->AFR[1] = 0xCCCCCCCC;\r
- /* Configure PHx pins in Alternate function mode */ \r
- GPIOH->MODER = 0xAAAA08A0;\r
- /* Configure PHx pins speed to 50 MHz */ \r
- GPIOH->OSPEEDR = 0xAAAA08A0;\r
- /* Configure PHx pins Output type to push-pull */ \r
- GPIOH->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PHx pins */ \r
- GPIOH->PUPDR = 0x55550450;\r
- \r
- /* Connect PIx pins to FMC Alternate function */\r
- GPIOI->AFR[0] = 0xCCCCCCCC;\r
- GPIOI->AFR[1] = 0x00000CC0;\r
- /* Configure PIx pins in Alternate function mode */ \r
- GPIOI->MODER = 0x0028AAAA;\r
- /* Configure PIx pins speed to 50 MHz */ \r
- GPIOI->OSPEEDR = 0x0028AAAA;\r
- /* Configure PIx pins Output type to push-pull */ \r
- GPIOI->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PIx pins */ \r
- GPIOI->PUPDR = 0x00145555;\r
- \r
-/*-- FMC Configuration ------------------------------------------------------*/\r
- /* Enable the FMC interface clock */\r
- RCC->AHB3ENR |= 0x00000001;\r
- \r
- /* Configure and enable SDRAM bank1 */\r
- FMC_Bank5_6->SDCR[0] = 0x000019E5;\r
- FMC_Bank5_6->SDTR[0] = 0x01116361; \r
- \r
- /* SDRAM initialization sequence */\r
- /* Clock enable command */\r
- FMC_Bank5_6->SDCMR = 0x00000011; \r
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
- while((tmpreg != 0) && (timeout-- > 0))\r
- {\r
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
- }\r
-\r
- /* Delay */\r
- for (index = 0; index<1000; index++);\r
- \r
- /* PALL command */\r
- FMC_Bank5_6->SDCMR = 0x00000012; \r
- timeout = 0xFFFF;\r
- while((tmpreg != 0) && (timeout-- > 0))\r
- {\r
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
- }\r
- \r
- /* Auto refresh command */\r
- FMC_Bank5_6->SDCMR = 0x000000F3;\r
- timeout = 0xFFFF;\r
- while((tmpreg != 0) && (timeout-- > 0))\r
- {\r
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
- }\r
- \r
- /* MRD register program */\r
- FMC_Bank5_6->SDCMR = 0x00046014;\r
- timeout = 0xFFFF;\r
- while((tmpreg != 0) && (timeout-- > 0))\r
- {\r
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r
- } \r
- \r
- /* Set refresh count */\r
- tmpreg = FMC_Bank5_6->SDRTR;\r
- FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));\r
- \r
- /* Disable write protection */\r
- tmpreg = FMC_Bank5_6->SDCR[0]; \r
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\r
-#endif /* DATA_IN_ExtSDRAM */\r
-\r
-#if defined(DATA_IN_ExtSRAM)\r
-/*-- GPIOs Configuration -----------------------------------------------------*/\r
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
- RCC->AHB1ENR |= 0x00000078;\r
- \r
- /* Connect PDx pins to FMC Alternate function */\r
- GPIOD->AFR[0] = 0x00CCC0CC;\r
- GPIOD->AFR[1] = 0xCCCCCCCC;\r
- /* Configure PDx pins in Alternate function mode */ \r
- GPIOD->MODER = 0xAAAA0A8A;\r
- /* Configure PDx pins speed to 100 MHz */ \r
- GPIOD->OSPEEDR = 0xFFFF0FCF;\r
- /* Configure PDx pins Output type to push-pull */ \r
- GPIOD->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PDx pins */ \r
- GPIOD->PUPDR = 0x55550545;\r
-\r
- /* Connect PEx pins to FMC Alternate function */\r
- GPIOE->AFR[0] = 0xC00CC0CC;\r
- GPIOE->AFR[1] = 0xCCCCCCCC;\r
- /* Configure PEx pins in Alternate function mode */ \r
- GPIOE->MODER = 0xAAAA828A;\r
- /* Configure PEx pins speed to 100 MHz */ \r
- GPIOE->OSPEEDR = 0xFFFFC3CF;\r
- /* Configure PEx pins Output type to push-pull */ \r
- GPIOE->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PEx pins */ \r
- GPIOE->PUPDR = 0x55554145;\r
-\r
- /* Connect PFx pins to FMC Alternate function */\r
- GPIOF->AFR[0] = 0x00CCCCCC;\r
- GPIOF->AFR[1] = 0xCCCC0000;\r
- /* Configure PFx pins in Alternate function mode */ \r
- GPIOF->MODER = 0xAA000AAA;\r
- /* Configure PFx pins speed to 100 MHz */ \r
- GPIOF->OSPEEDR = 0xFF000FFF;\r
- /* Configure PFx pins Output type to push-pull */ \r
- GPIOF->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PFx pins */ \r
- GPIOF->PUPDR = 0x55000555;\r
-\r
- /* Connect PGx pins to FMC Alternate function */\r
- GPIOG->AFR[0] = 0x00CCCCCC;\r
- GPIOG->AFR[1] = 0x000000C0;\r
- /* Configure PGx pins in Alternate function mode */ \r
- GPIOG->MODER = 0x00200AAA;\r
- /* Configure PGx pins speed to 100 MHz */ \r
- GPIOG->OSPEEDR = 0x00300FFF;\r
- /* Configure PGx pins Output type to push-pull */ \r
- GPIOG->OTYPER = 0x00000000;\r
- /* No pull-up, pull-down for PGx pins */ \r
- GPIOG->PUPDR = 0x00100555;\r
- \r
-/*-- FMC/FSMC Configuration --------------------------------------------------*/ \r
- /* Enable the FMC/FSMC interface clock */\r
- RCC->AHB3ENR |= 0x00000001;\r
-\r
- /* Configure and enable Bank1_SRAM2 */\r
- FMC_Bank1->BTCR[4] = 0x00001091;\r
- FMC_Bank1->BTCR[5] = 0x00110212;\r
- FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; \r
-\r
-#endif /* DATA_IN_ExtSRAM */\r
-}\r
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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