--- /dev/null
+ /**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief Header file of SPI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SPI_H\r
+#define __STM32F7xx_HAL_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Types SPI Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SPI Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_Mode */\r
+\r
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.\r
+ This parameter can be a value of @ref SPI_Direction */\r
+\r
+ uint32_t DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_Data_Size */\r
+\r
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+\r
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .\r
+ This parameter can be a value of @ref SPI_TI_mode */\r
+\r
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.\r
+ This parameter can be a value of @ref SPI_CRC_Calculation */\r
+\r
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */\r
+\r
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.\r
+ CRC Length is only used with Data8 and Data16, not other data size\r
+ This parameter can be a value of @ref SPI_CRC_length */\r
+\r
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .\r
+ This parameter can be a value of @ref SPI_NSSP_Mode\r
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and\r
+ it takes effect only if the SPI interface is configured as Motorola SPI\r
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r
+ CPOL setting is ignored).. */\r
+} SPI_InitTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */\r
+ HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */\r
+ HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */\r
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing*/\r
+ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */\r
+}HAL_SPI_StateTypeDef;\r
+\r
+/**\r
+ * @brief SPI handle Structure definition\r
+ */\r
+typedef struct __SPI_HandleTypeDef\r
+{\r
+ SPI_TypeDef *Instance; /* SPI registers base address */\r
+\r
+ SPI_InitTypeDef Init; /* SPI communication parameters */\r
+\r
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */\r
+\r
+ uint16_t TxXferSize; /* SPI Tx Transfer size */\r
+\r
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */\r
+\r
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */\r
+\r
+ uint16_t RxXferSize; /* SPI Rx Transfer size */\r
+\r
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */\r
+\r
+ uint32_t CRCSize; /* SPI CRC size used for the transfer */\r
+\r
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */\r
+\r
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /* Locking object */\r
+\r
+ HAL_SPI_StateTypeDef State; /* SPI communication state */\r
+\r
+ uint32_t ErrorCode; /* SPI Error code */\r
+\r
+}SPI_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants SPI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Error_Code SPI Error Code\r
+ * @{\r
+ */\r
+#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */\r
+#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */\r
+#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */\r
+#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */\r
+#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */\r
+#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */\r
+#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */\r
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknow Error error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SPI_Mode SPI Mode\r
+ * @{\r
+ */\r
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)\r
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Direction SPI Direction Mode\r
+ * @{\r
+ */\r
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)\r
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY\r
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Data_Size SPI Data Size\r
+ * @{\r
+ */\r
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300)\r
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400)\r
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500)\r
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600)\r
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700)\r
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800)\r
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900)\r
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)\r
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)\r
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)\r
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)\r
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)\r
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r
+ * @{\r
+ */\r
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000)\r
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase SPI Clock Phase\r
+ * @{\r
+ */\r
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)\r
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management\r
+ * @{\r
+ */\r
+#define SPI_NSS_SOFT SPI_CR1_SSM\r
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)\r
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r
+ * @{\r
+ */\r
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP\r
+#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r
+ * @{\r
+ */\r
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)\r
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)\r
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)\r
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)\r
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)\r
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)\r
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)\r
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission\r
+ * @{\r
+ */\r
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)\r
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_TI_mode SPI TI mode\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)\r
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r
+ * @{\r
+ */\r
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)\r
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_length SPI CRC Length\r
+ * @{\r
+ * This parameter can be one of the following values:\r
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit\r
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit\r
+ */\r
+#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)\r
+#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)\r
+#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r
+ * @{\r
+ * This parameter can be one of the following values:\r
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r
+ * RXNE event is generated if the FIFO\r
+ * level is greater or equal to 1/2(16-bits).\r
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r
+ * level is greater or equal to 1/4(8 bits). */\r
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH\r
+#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition\r
+ * @brief SPI Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define SPI_IT_TXE SPI_CR2_TXEIE\r
+#define SPI_IT_RXNE SPI_CR2_RXNEIE\r
+#define SPI_IT_ERR SPI_CR2_ERRIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SPI_Flag_definition SPI Flag definition\r
+ * @brief Flag definition\r
+ * Elements values convention: 0xXXXXYYYY\r
+ * - XXXX : Flag register Index\r
+ * - YYYY : Flag mask\r
+ * @{\r
+ */\r
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */\r
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */\r
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */\r
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */\r
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */\r
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */\r
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */\r
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */\r
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r
+ * @{\r
+ */\r
+#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)\r
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)\r
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)\r
+#define SPI_FTLVL_FULL ((uint32_t)0x1800)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r
+ * @{\r
+ */\r
+#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)\r
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)\r
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)\r
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+/** @defgroup SPI_Exported_Macros SPI Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SPI handle state\r
+ * @param __HANDLE__: SPI handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r
+\r
+/** @brief Enables or disables the specified SPI interrupts.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg SPI_IT_ERR: Error interrupt enable\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))\r
+\r
+/** @brief Checks if the specified SPI interrupt source is enabled or disabled.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __INTERRUPT__ : specifies the SPI interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r
+ * @arg SPI_IT_ERR: Error interrupt enable\r
+ * @retval The new state of __IT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Checks whether the specified SPI flag is set or not.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @param __FLAG__ : specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag\r
+ * @arg SPI_FLAG_CRCERR: CRC error flag\r
+ * @arg SPI_FLAG_MODF: Mode fault flag\r
+ * @arg SPI_FLAG_OVR: Overrun flag\r
+ * @arg SPI_FLAG_BSY: Busy flag\r
+ * @arg SPI_FLAG_FRE: Frame format error flag\r
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clears the SPI CRCERR pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r
+\r
+/** @brief Clears the SPI MODF pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Clears the SPI OVR pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->DR; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Clears the SPI FRE pending flag.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \\r
+ do{ \\r
+ __IO uint32_t tmpreg; \\r
+ tmpreg = (__HANDLE__)->Instance->SR; \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Enables the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)\r
+\r
+/** @brief Disables the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros --------------------------------------------------------*/\r
+/** @defgroup SPI_Private_Macros SPI Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Sets the SPI transmit-only mode.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)\r
+\r
+/** @brief Sets the SPI receive-only mode.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))\r
+\r
+/** @brief Resets the CRC calculation of the SPI.\r
+ * @param __HANDLE__ : specifies the SPI Handle.\r
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\\r
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)\r
+\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \\r
+ ((MODE) == SPI_MODE_MASTER))\r
+\r
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \\r
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\\r
+ ((MODE) == SPI_DIRECTION_1LINE))\r
+\r
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)\r
+\r
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \\r
+ ((MODE) == SPI_DIRECTION_1LINE))\r
+\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \\r
+ ((DATASIZE) == SPI_DATASIZE_4BIT))\r
+\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \\r
+ ((CPOL) == SPI_POLARITY_HIGH))\r
+\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \\r
+ ((CPHA) == SPI_PHASE_2EDGE))\r
+\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \\r
+ ((NSS) == SPI_NSS_HARD_INPUT) || \\r
+ ((NSS) == SPI_NSS_HARD_OUTPUT))\r
+\r
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \\r
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))\r
+\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\r
+\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\r
+ ((BIT) == SPI_FIRSTBIT_LSB))\r
+\r
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \\r
+ ((MODE) == SPI_TIMODE_ENABLE))\r
+\r
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \\r
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))\r
+\r
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\\r
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \\r
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SPI_Exported_Functions SPI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions \r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *****************************************************/\r
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r
+\r
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions \r
+ * @{\r
+ */\r
+\r
+/* Peripheral State and Error functions ***************************************/\r
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SPI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff