--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_sram.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief Header file of SRAM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_SRAM_H\r
+#define __STM32F7xx_HAL_SRAM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_ll_fmc.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+/** @addtogroup SRAM\r
+ * @{\r
+ */ \r
+\r
+/* Exported typedef ----------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Types SRAM Exported Types\r
+ * @{\r
+ */\r
+/** \r
+ * @brief HAL SRAM State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */\r
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */\r
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */\r
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */\r
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */\r
+ \r
+}HAL_SRAM_StateTypeDef;\r
+\r
+/** \r
+ * @brief SRAM handle Structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ \r
+ \r
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */\r
+ \r
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */ \r
+ \r
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */\r
+ \r
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */\r
+ \r
+}SRAM_HandleTypeDef; \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset SRAM handle state\r
+ * @param __HANDLE__: SRAM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization/de-initialization functions ********************************/\r
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);\r
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);\r
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions\r
+ * @{\r
+ */\r
+\r
+/* I/O operation functions ***************************************************/\r
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r
+\r
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions\r
+ * @{\r
+ */\r
+\r
+/* SRAM Control functions ****************************************************/\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);\r
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions\r
+ * @{\r
+ */\r
+\r
+/* SRAM State functions ******************************************************/\r
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_SRAM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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