--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_can.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief CAN HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Controller Area Network (CAN) peripheral:\r
+ * + Initialization and de-initialization functions \r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Error functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ (#) Enable the CAN controller interface clock using \r
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN1_CLK_ENABLE() for CAN2\r
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.\r
+ \r
+ (#) CAN pins configuration\r
+ (++) Enable the clock for the CAN GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE() \r
+ (++) Connect and configure the involved CAN pins to AF9 using the \r
+ following function HAL_GPIO_Init() \r
+ \r
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function. \r
+ \r
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.\r
+ \r
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission and wait the end of this operation \r
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout\r
+ according to his end application\r
+ (+) Start the CAN peripheral reception and wait the end of this operation \r
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout\r
+ according to his end application \r
+ \r
+ *** Interrupt mode IO operation *** \r
+ ===================================\r
+ [..] \r
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()\r
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() \r
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine\r
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback \r
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can \r
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback\r
+ \r
+ *** CAN HAL driver macros list ***\r
+ ============================================= \r
+ [..]\r
+ Below the list of most used macros in CAN HAL driver.\r
+ \r
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts\r
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts\r
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled\r
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags\r
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status\r
+ \r
+ [..] \r
+ (@) You can refer to the CAN HAL driver header file for more useful macros \r
+ \r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN CAN\r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+ \r
+#ifdef HAL_CAN_MODULE_ENABLED \r
+\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup CAN_Private_Constants\r
+ * @{\r
+ */\r
+#define CAN_TIMEOUT_VALUE 10\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup CAN_Exported_Functions CAN Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the CAN. \r
+ (+) De-initialize the CAN. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t InitStatus = 3;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));\r
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));\r
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));\r
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));\r
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));\r
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\r
+ \r
+\r
+ if(hcan->State == HAL_CAN_STATE_RESET)\r
+ { \r
+ /* Init the low level hardware */\r
+ HAL_CAN_MspInit(hcan);\r
+ }\r
+ \r
+ /* Initialize the CAN state*/\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* Exit from sleep mode */\r
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
+\r
+ /* Request initialisation */\r
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledge */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_INITSTATUS_FAILED;\r
+ }\r
+ else \r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (hcan->Init.TTCM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (hcan->Init.ABOM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (hcan->Init.AWUM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (hcan->Init.NART == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (hcan->Init.RFLM == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (hcan->Init.TXFP == ENABLE)\r
+ {\r
+ hcan->Instance->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \\r
+ ((uint32_t)hcan->Init.SJW) | \\r
+ ((uint32_t)hcan->Init.BS1) | \\r
+ ((uint32_t)hcan->Init.BS2) | \\r
+ ((uint32_t)hcan->Init.Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check acknowledged */\r
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_INITSTATUS_FAILED;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CAN_INITSTATUS_SUCCESS;\r
+ }\r
+ }\r
+ \r
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)\r
+ {\r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Initialize the CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR;\r
+ \r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the CAN reception filter according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that\r
+ * contains the filter configuration information.\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)\r
+{\r
+ uint32_t filternbrbitpos = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));\r
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));\r
+ \r
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;\r
+ \r
+ /* Select the start slave bank */\r
+ CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);\r
+ CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);\r
+ \r
+ /* Filter Deactivation */\r
+ CAN1->FA1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* Filter Scale */\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN1->FS1R &= ~(uint32_t)filternbrbitpos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);\r
+ }\r
+\r
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN1->FS1R |= filternbrbitpos;\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN1->FM1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN1->FM1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;\r
+ }\r
+\r
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN1->FFA1R |= (uint32_t)filternbrbitpos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (sFilterConfig->FilterActivation == ENABLE)\r
+ {\r
+ CAN1->FA1R |= filternbrbitpos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the CANx peripheral registers to their default reset values. \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Check CAN handle */\r
+ if(hcan == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY;\r
+ \r
+ /* DeInit the low level hardware */\r
+ HAL_CAN_MspDeInit(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the CAN MSP.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a CAN frame message.\r
+ (+) Receive a CAN frame message.\r
+ (+) Enter CAN peripheral in sleep mode. \r
+ (+) Wake up the CAN peripheral from sleep mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)\r
+{\r
+ uint32_t transmitmailbox = 5;\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = 0;\r
+ }\r
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = 1;\r
+ }\r
+ else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmitmailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ }\r
+\r
+ if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)\r
+ {\r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check End of transmission flag */\r
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_ERROR;\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t transmitmailbox = 5;\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r
+ \r
+ tmp = hcan->State;\r
+ if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Select one empty transmit mailbox */\r
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmitmailbox = 0;\r
+ }\r
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmitmailbox = 1;\r
+ }\r
+ else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmitmailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r
+ }\r
+\r
+ if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)\r
+ {\r
+ /* Set up the Id */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); \r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\r
+ hcan->pTxMsg->IDE | \\r
+ hcan->pTxMsg->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r
+\r
+ /* Set up the data field */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r
+ ((uint32_t)hcan->pTxMsg->Data[0]));\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r
+ ((uint32_t)hcan->pTxMsg->Data[4]));\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Enable Error warning Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Enable Error passive Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Enable Bus-off Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Enable Last error code Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Enable Error Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);\r
+ \r
+ /* Enable Transmit mailbox empty Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);\r
+ \r
+ /* Request transmission */\r
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: FIFO Number value\r
+ * @param Timeout: Specify Timeout value \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Get tick */ \r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Check pending message */\r
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)\r
+ {\r
+ /* Check for the Timeout */\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ \r
+ /* Release the FIFO */\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Release FIFO0 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ }\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ /* Release FIFO1 */\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ \r
+ tmp = hcan->State;\r
+ if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))\r
+ {\r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ \r
+ /* Set CAN error code to none */\r
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r
+ \r
+ /* Enable Error warning Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Enable Error passive Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Enable Bus-off Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Enable Last error code Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Enable Error Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);\r
+\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ if(FIFONumber == CAN_FIFO0)\r
+ {\r
+ /* Enable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ else\r
+ {\r
+ /* Enable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters the Sleep (low power) mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Request Sleep mode */\r
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ /* Wait the acknowledge */\r
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State = HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral\r
+ * is in the normal mode.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL status.\r
+ */\r
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hcan);\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY; \r
+ \r
+ /* Wake up request */\r
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Sleep mode status */\r
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r
+ {\r
+ hcan->State= HAL_CAN_STATE_TIMEOUT;\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hcan);\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles CAN interrupt request \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)\r
+{\r
+ uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;\r
+ \r
+ /* Check End of transmission flag */\r
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))\r
+ {\r
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);\r
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);\r
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);\r
+ if(tmp1 || tmp2 || tmp3) \r
+ {\r
+ /* Call transmit function */\r
+ CAN_Transmit_IT(hcan);\r
+ }\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);\r
+ /* Check End of reception flag for FIFO0 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO0);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);\r
+ /* Check End of reception flag for FIFO1 */\r
+ if((tmp1 != 0) && tmp2)\r
+ {\r
+ /* Call receive function */\r
+ CAN_Receive_IT(hcan, CAN_FIFO1);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Error Warning Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EWG error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;\r
+ /* Clear Error Warning Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Error Passive Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to EPV error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;\r
+ /* Clear Error Passive Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);\r
+ }\r
+ \r
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r
+ /* Check Bus-Off Flag */\r
+ if(tmp1 && tmp2 && tmp3)\r
+ {\r
+ /* Set CAN error code to BOF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;\r
+ /* Clear Bus-Off Flag */ \r
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);\r
+ }\r
+ \r
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);\r
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);\r
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r
+ /* Check Last error code Flag */\r
+ if((!tmp1) && tmp2 && tmp3)\r
+ {\r
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;\r
+ switch(tmp1)\r
+ {\r
+ case(CAN_ESR_LEC_0):\r
+ /* Set CAN error code to STF error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;\r
+ break;\r
+ case(CAN_ESR_LEC_1):\r
+ /* Set CAN error code to FOR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;\r
+ break;\r
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to ACK error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;\r
+ break;\r
+ case(CAN_ESR_LEC_2):\r
+ /* Set CAN error code to BR error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\r
+ /* Set CAN error code to BD error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;\r
+ break;\r
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\r
+ /* Set CAN error code to CRC error */\r
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Clear Last error code Flag */ \r
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);\r
+ }\r
+\r
+ /* Call the Error call Back in case of Errors */\r
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)\r
+ {\r
+ /* Set the CAN state ready to be able to start again the process */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ /* Call Error callback function */\r
+ HAL_CAN_ErrorCallback(hcan);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Transmission complete callback in non blocking mode \r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_RxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Error CAN callback.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval None\r
+ */\r
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_CAN_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions\r
+ * @brief CAN Peripheral State functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral State and Error functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to :\r
+ (+) Check the CAN state.\r
+ (+) Check CAN Errors detected during interrupt process\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief return the CAN state\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval HAL state\r
+ */\r
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Return CAN state */\r
+ return hcan->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the CAN error code\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN.\r
+ * @retval CAN Error Code\r
+ */\r
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\r
+{\r
+ return hcan->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @brief Initiates and transmits a CAN frame message.\r
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r
+{\r
+ /* Disable Transmit mailbox empty Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)\r
+ { \r
+ /* Disable Error warning Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Disable Error passive Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Disable Bus-off Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Disable Last error code Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Disable Error Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_RX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+ \r
+ /* Transmission complete callback */ \r
+ HAL_CAN_TxCpltCallback(hcan);\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Receives a correct CAN frame.\r
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains\r
+ * the configuration information for the specified CAN. \r
+ * @param FIFONumber: Specify the FIFO number \r
+ * @retval HAL status\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r
+{\r
+ /* Get the Id */\r
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)\r
+ {\r
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r
+ \r
+ /* Disable FIFO 0 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r
+ \r
+ /* Disable FIFO 1 message pending Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)\r
+ { \r
+ /* Disable Error warning Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);\r
+ \r
+ /* Disable Error passive Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);\r
+ \r
+ /* Disable Bus-off Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);\r
+ \r
+ /* Disable Last error code Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);\r
+ \r
+ /* Disable Error Interrupt */\r
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);\r
+ }\r
+ \r
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r
+ {\r
+ /* Disable CAN state */\r
+ hcan->State = HAL_CAN_STATE_BUSY_TX;\r
+ }\r
+ else\r
+ {\r
+ /* Change CAN state */\r
+ hcan->State = HAL_CAN_STATE_READY;\r
+ }\r
+\r
+ /* Receive complete callback */ \r
+ HAL_CAN_RxCpltCallback(hcan);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff