--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 24-March-2015\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWR_Private_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */ \r
+#define PVD_MODE_IT ((uint32_t)0x00010000)\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000)\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r
+ * @{\r
+ */ \r
+#define PWR_EWUP_MASK ((uint32_t)0x00003F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted \r
+ write accesses. \r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ \r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a \r
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r
+ than the PVD threshold. This event is internally connected to the EXTI \r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** Wake-up pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r
+ forced in input pull-down configuration and is active on rising edges.\r
+ (+) There are to 6 Wake-up pin in the STM32F7 devices family\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The devices feature 3 low-power modes:\r
+ (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator \r
+ in low power mode\r
+ (+) Standby mode: 1.2V domain powered off.\r
+ \r
+ *** Sleep mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ \r
+ -@@- The Regulator parameter is not used for the STM32F7 family \r
+ and is kept as parameter just to maintain compatibility with the \r
+ lower power families (STM32L).\r
+ (+) Exit:\r
+ Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Stop mode ***\r
+ =================\r
+ [..]\r
+ In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents \r
+ are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, FLASH can be powered off before \r
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r
+ It can be switched on again by software after exiting the Stop mode using\r
+ the HAL_PWREx_DisableFlashPowerDown() function. \r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r
+ function with:\r
+ (++) Main regulator ON.\r
+ (++) Low Power regulator ON.\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ (+)\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r
+ The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r
+ the HSE oscillator are also switched off. SRAM and register contents are lost \r
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby \r
+ circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ (++) Entry:\r
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (++) Exit:\r
+ (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ \r
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event or a time-stamp event, without depending on \r
+ an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r
+ \r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+ \r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each \r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+ \r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r
+ \r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+ \r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+ \r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+ \r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values, which sets the default polarity: \r
+ * detection on high level (rising edge):\r
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r
+ * or one of the following value where the user can explicitly states the enabled pin and\r
+ * the chosen polarity \r
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+ \r
+ /* Enable wake-up pin */\r
+ SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r
+ \r
+ /* Specifies the Wake-Up pin polarity for the event detection\r
+ (rising or falling edge) */\r
+ MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r
+}\r
+\r
+/**\r
+ * @brief Disables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3\r
+ * @arg PWR_WAKEUP_PIN4\r
+ * @arg PWR_WAKEUP_PIN5\r
+ * @arg PWR_WAKEUP_PIN6 \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r
+}\r
+ \r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * \r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r
+ * systick interrupt when used as time base for Timeout \r
+ * \r
+ * @param Regulator: Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @note This parameter is not used for the STM32F7 family and is kept as parameter\r
+ * just to maintain compatibility with the lower power families.\r
+ * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters Stop mode. \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Select the regulator state in Stop mode ---------------------------------*/\r
+ tmpreg = PWR->CR1;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r
+ \r
+ /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r
+ tmpreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tmpreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r
+}\r
+\r
+/**\r
+ * @brief Enters Standby mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r
+ * Alarm out, or RTC clock calibration out.\r
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. \r
+ * - WKUP pins if enabled. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Select Standby mode */\r
+ PWR->CR1 |= PWR_CR1_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+ /* Check PWR Exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+ \r
+ /* Clear PWR Exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enables CORTEX M4 SEVONPEND bit. \r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables CORTEX M4 SEVONPEND bit. \r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r